Agenda, EDI CON IBIS Summit Meeting
September 13, 2017 13:00-17:00
Hynes Convention Center
900 Boylston St
Boston, Massachusetts
| SPONSORS: | SiSoft Teraspeed Labs |
| (Minutes | Zip download of all files) | |
| 12:00 | FREE LUNCH (with EDI CON Exhibits and IBIS registration) |
| 13:00 | SIGN IN |
| 13:10 | WELCOME AND INTRODUCTIONS
Mike LaBonte (SiSoft) |
| 13:15 | IBIS Update
Mike LaBonte (SiSoft) |
| 13:30 | Leveraging IBIS Capabilities for Multi-Gigabit Interfaces
Ken Willis (Cadence Design Systems) |
| 14:00 | Addressing DDR5 Design Challenges with IBIS-AMI Modeling Techniques
Todd Westerhoff, Doug Burns, Eric Brock (SiSoft) [Presented by Todd Westerhoff, (SiSoft)] |
| 14:45 | BREAK, REFRESHMENTS (30 Minutes) |
| 15:15 | Interconnect Modeling Using IBIS-ISS and Touchstone
Michael Mirmak (Intel Corporation) [Presented by Mike LaBonte (SiSoft)] |
| 15:45 | IBIS-AMI Dual Models: Why the Jitters?
Mike LaBonte (SiSoft) |
| 16:30 | OPEN DISCUSSION |
| 16:50 | CLOSING REMARKS Mike LaBonte (SiSoft) |
| 17:00 | END OF MEETING |