Minutes, IBIS Quality Committee

21 Apr 2015

11:00-12:00 EST (08:00-09:00 PST)

ROLL CALL

eASIC:                              David Banas
Ericsson:                           Anders Ekholm
Intel:                              Michael Mirmak
                                    Eugene Lim
IO Methodology                      Lance Wang
Signal Integrity Software         * Mike LaBonte
Teraspeed Labs:                   * Bob Ross

Everyone in attendance marked by *

NOTE: "AR" = Action Required.

-----------------------MINUTES ---------------------------
Mike LaBonte conducted the meeting.

Call for IBIS related patent disclosures:

- None

Call for opens:

- Bob: There is a parser development issue to discuss.

ARs:

- Mike produce code snippets related to completely empty message comments.
  - Progress made but not done yet.

- Mike recover percent format specifications in spreadsheet.
  - No new progress.

- Mike add comments to CMPNT, DLY, MSPEC sections.
  - No new progress.

- Lance add comments to EBD section.
  - No new progress.

- Bob add comments to CIRCUIT section.
  - No new progress.


Parser development:

- Bob showed a presentation related to the BIRD 175 draft.
- slide 7:
  - Bob: This depicts how pins and pads will be connected with [Merged Pins].
    - In the second part the GND pads are all joined because they are part of a [Pin Mapping] bus.
- slide 8:
  - Bob: This shows an illegal case that the parser has to look for.
    - The Vcc [Merged Pins] here are mapped to different [Pin Mapping] buses.
    - The GND side shows pins implicitly added to a [Merged Pins].
  - Mike: This might cause errors if model makers create package models for only the listed pins.
    - Two approaches are possible:
      - Implicitly include all pins on the bus.
      - Make it illegal to not specify all pins from the bus.
    - Bob: Or it could fall through to RLC.
      - We never want to have anything floating.
      - We are covering cases where the component [Pin Mapping] doesn't align with the [Package Model].
      - If [Pin Mapping] doesn't exist we are stuck.
- slide 6:
  - Bob: This shows a case with no [Pin Mapping].
  - Mike: It looks like the Vcc pads are mostly floating.
  - Bob: This has to be considered carefully.
  - Mike: We should not leave anything floating nor synthesize unspecified connections.
    - One rule should be that [Merged Pins] shorts the same lists of pins and pads together.
    - And [Pin Mapping] can short the pad groups together.

- Bob showed the BIRD 175 rules drafted for the parser developer.
- Bob: This use terms "merging pin" and "merged pin".
  - There are 5 [Merged Pins] rules that produce error conditions.
  - These completely define a good model.
  - There are 4 [Pin Mapping] rules.
    - These need to be reworded to indicate failure conditions.
  - We need language for when [Merged Pins] doesn't work with [Pin Mapping] bus structures.
- Mike: The word "incompatible" might help.
- Bob: A re-layout of the chip may change bus structures.
- Mike: The term "merged pins" can be confused with [Merged Pins].
- Bob: That needs work.
  - The parser will have to store these lists for checking later.

Meeting ended: 12:03

Next meeting April 28