DATE: 06/21/05
SUBJECT: June 14, 2005 EIA IBIS Open Forum Summit Minutes
VOTING MEMBERS AND 2005 PARTICIPANTS
Actel Prabhu Mohan*
Agere (Nirav Patel)
AMD Wasim Ullah
Ansoft Corporation Michael Brenneman
Applied Simulation Technology Norio Matsui
Cadence Design Systems Lance Wang*, [Donald Telian],
Heiko Dudek, Shangli Wu,
Dragoslav Milosevec*, Ken Willis*
Cisco Systems Syed Huq*, Mike LaBonte,
Todd Westerhoff*, Zhiping Yang*,
Vinu Armumugham,
Salman Jiva, Satish Pratapneni,
Il-young Park, Sergio Camerlo,
Phillipe Sochoux, Eddie Wu,
Gurpreet Hundal, Jayanthi Natarajan
AbdulRahman Rafiq
Fluent (Chetan Desai)
Freescale Jon Burnett
Hitachi ULSI Systems Kazuyoshi Shoji*
Huawei (Jiang Xiang Zhong)
IBM (Wesley Martin), H. John Beatty*
Integrated Circuit Systems (ICS) (Dan Clementi)
Intel Corporation Michael Mirmak*, Arpad Muranyi*,
Suresh Chandrasekhar*
LSI Logic Frank Gasparik, William Lau*,
Mike Jenkins*, Reginald Cowley*,
Kusumakumari Matta*
Marvell Itzik Peleg
Mentor Graphics John Angulo, Guy de Burgh, Ian Dodd*,
Steven McKinney, Kim Owen,
Stephane Rousseau
Micron Technology Randy Wolff, Paul Gregory
NEC Electronics Corporation Takeshi Watanabe*, Lori Askew*,
Takuro Tsujikawa
Panasonic Atsuji Ito*
Samtec [Otto Bennig]
Siemens AG Eckhard Lenski, Katja Koller
Manfred Maurer, Heinz Ibowski,
Wolfgang Rohmer, Klaus Huebner
Michael Kindij
Siemens Medical David Lieby
Signal Integrity Software Robert Haller, Douglas Burns,
Barry Katz, Mike Mayer
Sigrity Sam Chitwood*, Jing Ting, Raymond Chen*
Jiaguan Fang, Teo Yatman
Silego (Joe Froniewski)
Silicon Image (Ook Kim)
Synopsys Warren Wong*, Andy Tai*
Teraspeed Consulting Group Bob Ross*, Scott McMorrow,
Tom Dagostino
Texas Instruments (Jean Claude Perrin)
Xilinx Ray Anderson, Sanjay Mehta
Zuken Michael Schaeder, Ralf Bruening
OTHER PARTICIPANTS IN 2005:
Altera Khalid Ansari
Bayside Design Kevin Roselle
CelsioniX Kellee Crisafulli
Dell Aubrey Sparkman
EMC Brian Arsenault, Daniel Nilsson,
Jason Pritchard, Jinhua Chen
Enterasys Networks Fabrizio Zanella
EPFL Alain Vachoux
Fujitsu Siemens Computers Martin Ramme
GEIA (Chris Denham)
Green Streak Programs Lynne Green*
Infineon Technologies AG Thomas Steinecke, Minea Gospodinova,
Amir Motamedi, Yann Zinsius,
Christian Sporrer, Radovan Vuletic
INSA Toulouse Etienne Sicard
JMD International Joe Socha*
KAW Kazuhiko Kusunoki
Leventhal Design Roy Leventhal
NetLogic Eric Hsu
Nokia Erno Lahteenmati*, Tapan von Ravner*
North Carolina State Univ. Ambrish Varma
Politecnio di Torino Igor Stievano
Si2 Sumit DasGupta*
Silicon Bandwidth [Kim Helliwell]
Sun Microsystems Gustavo Blando
Time Domain Analysis Systems Dima Smolyansky, Steve Corey
Western Digital Mohammad Ali
Independent Bernhard Unger (Siemens retired),
Kim Helliwell*
In the list above, attendees at the meeting are indicated by *.
Principal members or other active members who have not attended are in
parentheses. Participants who no longer are in the organization are in
square brackets.
UPCOMING MEETINGS
The bridge numbers for future IBIS teleconferences are as follows:
Date Telephone Number Bridge # Passcode
June 24, 2005 1-916-356-2663 4 815-0120
All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas
are typically distributed seven days before each Open Forum. Minutes
are typically distributed within seven days of the corresponding
meeting. When calling into the meeting, provide the bridge number and
passcode at the automated prompts. If asked by an operator, please
request to join the IBIS Open Forum hosted by Michael Mirmak.
For international dial-in numbers, please contact Michael Mirmak.
NOTE: "AR" = Action Required.
--------------------------------MINUTES---------------------------------
INTRODUCTIONS AND MEETING QUORUM
The IBIS Open Forum Summit was held in Anaheim, California at the
Anaheim Marriott during the 2005 Design Automation Conference (DAC).
31 people representing 17 organizations attended.
The notes below capture some of the content and discussions. The
meeting presentations and other documents are uploaded at:
http://www.ibis-information.org/summits/jun05/
Michael Mirmak opened the meeting. Michael thanked co-sponsors Cadence
Design Systems and Mentor Graphics for their financial and logistical
support. Michael also thanked the presenters and participants for
attending.
Michael asked everyone in the room to introduce themselves. The meeting
was well-attended by a cross-section of the IBIS community, including
semiconductor vendors, service providers, EDA tool vendors, and IBIS
users.
Michael asked if there were any new issues or discussion items to add to
the agenda. No issues were raised.
PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions.
These notes capture some of the content and discussion. More details
are available in the documents uploaded to the location noted above.
IBIS CHAIR'S REPORT AND ROADMAP
Michael Mirmak, Intel Corporation
Michael Mirmak summarized the current state of the IBIS Open Forum and
its activities. IBIS membership stands at 27, with several member
renewals anticipated. IBIS and ICM parser activities have been at a
high pace over the past few months. The JEITA-IBIS Conference in Tokyo
attracted 40 participants and paved the way for greater IBIS interaction
in Asia.
Michael also presented an updated timeline for IBIS development. The
IBIS 4.0 cookbook is expected to be complete within the next two
months. Similarly, the ICM 1.1 specification is expected to be
presented for an approval vote within the same period.
Key issues for the long term include the linking of ICM and IBIS and
the proper definition of IBIS 4.2 versus IBIS 5.0. A version 4.2 which
supported major changes would increase parser development costs to the
Open Forum without opening new sources of income.
Finally, Michael thanked the members and current officers -- Syed Huq,
Randy Wolff, Lance Wang and Bob Ross -- for their help in "making IBIS
happen" over the past year.
Lynne Green noted that the budget includes significantly more outlays
than current income. Michael responded with a brief summary of major
IBIS expenditures. Parser license fees are spent only on parser
development and not on other purposes. Membership fees are used to
support the regular operation of the IBIS Open Forum, including paying
for the DAC Summit and other summit expenses, reproduction fees and the
like. Most of the membership dues are paid in turn to the GEIA, which
provides accounting and legal services to the Open Forum and supports
the ANSI balloting process. Michael noted that additional memberships
are still being processed and that the new ICM license arrangements
would likely generate additional income to make up the deficit.
LIBRARY CHARACTERIZATION AND MODELING: ISSUES RECOMMENDATIONS
AND POSSIBLE SOLUTIONS
Sumit DasGupta, Si2 and H. John Beatty, IBM
Sumit DasGupta presented a brief summary of the mission and goals
of the Silicon Integration Initiative (Si2). As design sizes
increase but transistor sizes decrease, common problems with libraries
for silicon design are becoming evident. These include issues with
model accuracy (user-definable models, consistency across libraries,
etc.), library formatting consistency, tool requirements and the
overall capabilities of the model library data. To resolve these
issues, Si2 is assembling a new coalition of organizations to
create an Open Model library standard. Summit attendees were invited
to a meeting of the group to take place later at DAC.
Several participants inquired about the relevancy of the coalition to
IBIS. Both Lynne Green and Michael Mirmak noted that issues with
transistor-level models, formats, libraries and the like were
affecting the perception of IBIS in terms of accuracy. Further,
IBIS, as a modeling standard, would have a place in such a library
initiative representing a widespread I/O buffer model format.
POWER INTEGRITY PROPOSAL REGARDING BIRD95
Lance Wang and Ken Willis, Cadence Design Systems
Ken Willis summarized the state of BIRD95, noting that the proposal
was a "big deal" to the IBIS community. However, Ken observed that
the BIRD is focused on a pin-level or buffer-level approach. In
contrast, Ken proposed a component-level perspective, using a grid model
of buffers. Power delivery and simultaneous switching noise could be
analyzed as separate phenomena, with power delivery details -- rails and
connectivity -- established through a component-level grid model with
specific data on parasitic linking of portions of the grid.
Simultaneous switching would be described explicitly, with actual or
statistical information included in the IBIS file on the number of
buffers switching together. Zhiping Yang and Syed Huq objected that
separating pre-driver effects from I/O currents is very difficult to do
without detailed design information, particularly from lab data.
Lance Wang then analyzed several cases where the BIRD95
[Composite Current] keyword may not be adequate for unambiguously
describing switching effects. From the simulation waveforms presented,
Lance suggested that the relationship between local power and ground
would need to be specified using a composite current. Further,
scaling of current tables versus load does not always result in
accurate results. Most of all, the summing of static currents
assumed in using composite currents does not account for charge storage.
ELECTION OF OFFICERS
Michael Mirmak announced the positions and the existing slate of
nominees. Without dissent, the following candidates were elected by
the voting membership as officers for 2005-2006:
Chair: Michael Mirmak, Intel Corp.
Vice-Chair: Syed Huq, Cisco Systems
Secretary: Randy Wolff, Micron Technology
Postmaster: Bob Ross, Teraspeed Consulting Group
Webmaster: Syed Huq, Cisco Systems
Librarian: Lance Wang, Cadence Design Systems
Michael thanked the outgoing officers and congratulated the new officers.
Michael presented some commemorative items to the 2004-2005 board
members, and Syed Huq presented one to Michael. Michael then presented
a special commemorative award to Atsuji Ito of Panasonic, for his service
as the JEITA representative to IBIS and chair of the EDA Working Group.
MULTI-BUFFER SSN SIMULATION USING BIRD95
Zhiping Yang and Ilyoung Park, Cisco Systems, Inc.
Zhiping Yang summarized the state of BIRD95. The BIRD
adds new keywords to handle total current through the
power supply node. The power supply path is modeled through
ICM or a similar interconnect representation. Gate modulation
is handled through BIRD97/98, while crossbar current will
be addressed separately in the future.
The key concepts behind the BIRD involve creating current
versus time tables for IBIS alone, IBIS plus the power supply
interconnect path, and other variations and condition corners.
Zhiping showed simulation test results for a four buffer system with a
variety of switching conditions. Waveforms were compared between
simulations using IBIS alone, SPICE transistor models and IBIS
plus BIRD95. Correlation of buffer output and power supply
noise between IBIS plus BIRD95 and SPICE is very good for few
buffers switching, but worsens with greater numbers of buffers
switching simultaneously.
Todd Westerhoff noted that current shunting, even if huge, will
not have a noticeable effect on the power supply when switching low,
as the ground is ideal. This objection was addressed later;
the use of ideal ground is appropriate if the power supply netlist
includes the entire power and ground supply loop inductance and
related parasitics. Ken Willis suggested using a circuit approach
to power delivery analysis, as up to 18 current versus time tables
would be difficult to generate and process. Bob Ross noted that
this would not address collection of data in the lab, where a circuit
representation would not be available. Bob also noted that the
current tables should be time-correlated to the voltage versus
time tables of the buffer output. Syed Huq responded to several
comments by noting that BIRD95 only covers simultaneous switching
effects at the buffer level, with on-die effects ignored for the
moment. BIRD95 is not a unified solution for all power delivery
analysis needs.
MULTI-GIGABIT SERDES SYSTEM LEVEL ANALYSIS USING IBISV4.1 (VHDL-AMS)
Syed Huq, Cisco Systems and Ian Dodd, Mentor Graphics
Syed Huq summarized recent Cisco work on analyzing a XAUI serial-
differential system using buffers modeled using IBIS 4.1. The design
uses one tap pre-emphasis and receive equalization. The equalization
of the receiver relies upon two amplifiers modeled using polynomial
curve-fitting. The total speed of the system is 3.125 Gbps. Using
IBIS 4.1 VHDL-AMS models, jitter correlation between the SPICE and
behavioral models can be achieved to within 4 ps. Waveform correlation
between the SPICE, behavioral and lab results shows excellent edge
matching, but some differences between amplitudes, particularly at
higher levels of pre-emphasis. CPU times were approximately
141 times faster for the behavioral model versus the transistor-level
model.
Ian Dodd summarized the tool approach to modeling the system, including
the package, buffers, system interconnect and connectors. Agilent
Touchstone* files, Synopsys HSPICE* code and The Mathworks Matlab* plus
transfer functions were used to model the full system. The same
Touchstone* file was used for both channel paths outside the buffers.
Todd Westerhoff inquired about whether S-parameters actually slow down
simulations as the size of the S-parameter matrix increases. Ian Dodd
responded that this slow down is likely due to algorithm and/or
implementation details.
In response to the presentation's list of references, Lynne Green noted
that a Verilog-AMS book, called the Designer's Guide to Verilog-AMS by
Ken Kundert of Cadence Design Systems, was recently published.
IBIS 4.1 MACROS FOR SIMULATOR INDEPENDENT MODELS
Arpad Muranyi, Intel Corporation
Arpad Muranyi summarized recent controversies involving using the SPICE
in addition to or instead of the AMS languages supported in IBIS 4.1 for
modeling of complex structures. SPICE macromodels rely on a basic
IBIS element, similar to the Synopsys HSPICE* B-element, with additional
circuit structures like controlled sources to create complex designs.
Arpad suggested that tool vendors, model authors and model users were
confronted with difficult choices in deciding between AMS, SPICE
macromodeling or proprietary approaches in modeling today's designs.
To alleviate this, Arpad suggested a new approach where a common library
of device primitives is made publicly available. This library, which
would include basic "building blocks" such as resistors, current
sources, etc., would be written in AMS languages but with SPICE
structures in mind. Such a library could then be used by tools without
AMS support, as SPICE elements could be substituted for the existing AMS
primitives.
From this primitives library, a more abstract library of standard
macromodels could be created, to cover common designs such as pre-
emphasis and differential buffers, etc. Both libraries would be made
publicly available as templates to allow insertion of design-specific
data.
Todd Westerhoff suggested that a work group be established for
creating the macromodeling templates. Arpad and Todd will work offline
with Michael Mirmak to create such a group.
THINGS YOU CAN LEARN FROM V/I CURVES
Todd Westerhoff, Cisco Systems
Todd Westerhoff reviewed several basic techniques for analyzing IBIS
buffer performance using only DC information. Todd illustrated that the
majority of a buffer's operating time is spent in a DC state, while only
a fraction of simulation time is spent by the buffer in transition
between states.
Therefore, the series termination impedance required for matching a
driving buffer to a transmission line and the minimum current needed to
drive the line can be calculated simply from the load-line intercept of
the buffer. Overshoot and undershoot effects can be minimized by
correct termination selection based on the DC table information in the
IBIS file. Todd used an HSTL buffer design example to demonstrate the
system SI impact of poor buffer design and both proper and improper
termination selection.
JEITA-IBIS JOINT MEETING REPORT IN JAPAN & ASIAN IBIS SUMMIT
Takeshi Watanabe, NEC, Chair of JEITA EDA Working Group
Takeshi Watanabe presented a brief summary of the March JEITA-IBIS
meeting in Tokyo and also a proposal for future IBIS-related meetings
in Asia. The JEITA EDA Working Group exists to coordinate
standardization of the EDA treatment of a number of different system
components, including passive devices, cables, connectors and
active LSI designs. The group now includes 16 major companies as
members, including recent member Cadence Design Systems of Japan.
Takeshi summarized the recent JEITA-IBIS conference at JEITA HQ
on March 24, 2005. Presentations included a roadmap summary from
Michael Mirmak, an overview of complex I/O modeling using IBIS by
Lance Wang and an example of serdes modeling using IBIS 4.1 by
Syed Huq. JEITA members presented on EMI simulation and modeling
plus noise analysis. Response from JEITA attendees to the meeting
contents was overwhelmingly positive. As a result, JEITA would
like to propose a regular set of JEITA-IBIS meetings, perhaps every
March, starting in 2006 with US IBIS Open Forum participation.
ASIAN IBIS SUMMIT
Bob Ross, Teraspeed Consulting Group
Bob Ross summarized several recent events regarding IBIS in Asia.
Very good response has been noted worldwide to the JEITA-IBIS meeting
in Tokyo. IBIS Open Forum member Huawei has proposed sponsoring an
open Asian IBIS Summit in Shenzhen, People's Republic of China in
December 2006. This summit would be open to the public per EIA rules
and would last two days. Material would consist of standard summit
technical development presentations plus workshop and/or tutorial
information for newer engineers.
Bob observed that co-sponsorship and support -- financial and logistical
-- is still needed for this event to be successful. However, interest
is so high that this event could be the largest ever IBIS Summit.
Attendance estimates have ranged as high as 200 people. Several IBIS
Open Forum member companies have branch offices in the Shenzhen
economic zone or in nearby areas. Travel to the region is fairly
straightforward. Those interested in assisting with the event are
encouraged to contact Bob Ross.
AD HOC PRESENTATION: CALL FOR BOOK REVIEWERS
Lynne Green, Green Streak Programs
Lynne Green presented an example table of contents from a forthcoming
book on modeling and system analysis coauthored by her and Roy
Leventhal. She suggested that many technical book publishers and
authors are seeking independent reviewers to provide technical
and stylistic suggestions for improvement before publication. Those
interested in this opportunity may contact Lynne for a list of
publishing company contacts.
AD HOC PRESENTATION: THE MYTH OF GROUND BOUNCE
Sam Chitwood, Sigrity
In response to several statements regarding power delivery
analysis, Sam Chitwood presented on power delivery ground bounce
and ground bounce measurement concepts. Sam noted that many
system designers analyze ground bounce in reference to an ideal
"node zero" as used in SPICE tools or between the buffer local
reference and a printed circuit board reference. Sam suggested that
both these approaches are inappropriate. Node zero has no
physical meaning in a real system. Measuring ground bounce between
widely separated references is also meaningless. Sam emphasized
that voltage is a relative concept, comparing energy between
two physical points. For ground bounce, the voltage between
local power and local ground for the buffer is the critical
issue.
Tied to these misconceptions is partial inductance. In many cases,
inductances are added arbitrarily to power and ground nets for
power delivery simulations. The added devices are usually only
partial inductances, inserted without regard to total loop inductance.
The only appropriate inductances to use in power and ground simulations
are total loop inductances. S-parameters can be used for power
delivery simulations with a single ground reference, so long as the
reference is understood not to correspond to a physical system location.
Further, inductors can be added to the power and ground paths in
system netlists, if the inductance values correspond to the total
loop and not just to partial inductances.
OPEN DISCUSSION
Todd Westerhoff continued an earlier question regarding certification
of IBIS specification revision and feature support by EDA tool vendors.
Representatives of EDA vendors noted that, for business reasons, open
statements of feature support or lack of support is not always
desirable. Bob Ross also observed that the IBIS Open Forum should not
make public statements of certification regarding the IBIS specification
and specific vendor tools, particularly those of members. The team
reached consensus that the IBIS Quality and Model Review Subcommittees
can help to produce a "checklist" of specification features based on
the IBIS 4.1 tree diagram. This checklist could be coupled with a set
of validation models illustrating the features in an evaluation kit for
individuals to use when analyzing tools. Todd agreed to start
assembling this kit through these subcommittees.
Michael made a few brief observations about linking ICM and IBIS, noting
that the apparent restriction on "one to one" mapping between buffers
and pins under the [Pin] keyword is the most serious restriction. A
proposal to solve this problem is being written into a BIRD for
consideration by the Futures Subcommittee.
CONCLUDING ITEMS
Michael Mirmak again thanked the presenters, supporters, and sponsors
for their help and support in making the Summit a success. After
reminding the participants regarding the next Open Forum teleconference,
Michael closed the IBIS Summit Meeting.
OPENS FOR NEW ISSUES
None.
NEXT MEETING
The next IBIS Open Forum teleconference will be held June 24, 2005 from
8:00 AM to 10:00 AM US Pacific Time. A vote is scheduled for BIRD94.1.
========================================================================
NOTES
IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046
michael.mirmak@intel.com
Senior Analog Engineer, Intel Corporation
FM6-45
1900 Prairie City Rd.
Folsom, CA 95630
VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475
rrwolff@micron.com
Simulation Engineer, Micron Technology, Inc.
8000 S. Federal Way
Mail Stop: 1-711
Boise, ID 83707-0006
LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363
lwang@cadence.com
Senior Member, Technical Staff, Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA 01824
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400
bob@teraspeed.com
Staff Scientist, Teraspeed Consulting Group
10238 SW Lancaster Road
Portland, OR 97219
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