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IBIS INTERCONNECT TASK GROUP
http://www.ibis.org/interconnect_wip/
Mailing list: ibis-interconnect@freelists.org
Archives at http://www.freelists.org/archive/ibis-interconn/
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Attendees from June 22 Meeting (* means attended at least using audio)
ANSYS Curtis Clark
Cadence Design Systems Bradley Brim
Cisco David Siadat
Intel Corp. Michael Mirmak*
Keysight Technologies Radek Biernacki, Ming Yan
Mentor Graphics Arpad Muranyi*
Micron Technology Justin Butterfield*, Randy Wolff*
SAE ITC Maureen Lemankiewicz, Logen Johnson
Signal Integrity Software Walter Katz*, Mike LaBonte*
Teraspeed Labs Bob Ross*
University of Aveiro in Portugal Wael Dghais
Michael Mirmak convened the meeting. No patents were declared.
During opens, Michael mentioned that the June 15 minutes are missing,
possibly permanently, due to a computer change. If the draft minutes
can be found and sent out, he will do so. Bob Ross noted that he had
sent out updated examples for the Interconnect proposal draft. If
errors are found, corrections need to be part of the overall document
review.
Walter Katz asked about Brad Brim’s presentation on the Touchstone
shortcut. Michael replied that he had not received an update from
Brad, but will check with him again. Walter noted that this is the
last major technical issue remaining unresolved in the proposal.
Bob added that another pending issue is documentation for Package
Sets. These need formal specification and review in the document.
Walter presented on Commonly Supported Package Sets. He suggested
four levels exist:
1) Signal integrity on each pin alone is of interest
2) Crosstalk on each pin is of interest
3) Power delivery distribution models are of interest
4) Integrated power and SI coupled models are of interest
This implies additional facts for each level:
1) Distributed lossy models for each I/O pin for SI
2) Each I/O is a victim
3) Power and SI are modeled
4) Everything is modeled – power and signal integrity, plus
coupling
Rules for each are included in Walter’s presentation. He suggested
that these can be added to the specification, to the cookbook, or
simply be adopted in the industry by EDA agreement. Bob asked whether
rules for power delivery networks alone, without SI, should be
documented. Walter replied that there is no implication of this
situation in the rules. There should be no pathological sets
documented. Walter added that SiSoft is willing to agree to these
rules as written.
Michael asked whether there is any need to model PD networks only,
vs. SI and PD networks together. Walter replied no. Michael asked
whether a Cookbook rather than specification is needed simply to
avoid investigating pathological cases for completeness? Walter
confirmed this, adding that no names or keywords would be included
formally in the document.
Walter added that the team needs more EDA vendors to participate.
Walter will ask EDA vendors about the issues, along with updated
slides to the Interconnect list. Michael will “pile on” with
additional comments. Mike LaBonte will send the slides to other
vendors and post the slides.
Bob presented his updated examples – 12 in all. The names are just
instances; anyone can use any names they wish. The “I/O” term is
not always included, but assumed except when there’s a modifier.
Example 1 is identical to the current Interconnect set. Example 2
uses power and ground connections. Example 3 uses S2P for the buffer,
with pulldown_ref as the reference terminal, matching the provided
drawings. Mike LaBonte offered to remove this example and drawing
if this is a pathological example.
Example 4 includes buffer, pad, and pin, with a mixture of Touchstone
and IBIS-ISS models, but no PD network. Michael asked whether this
likely or possible. Bob replied that, yes, it can happen, though
the naming may be wrong on this example. Randy Wolff asked, if we
have some capacitance in a SPICE model, what’s the second terminal
to be used? Would someone put in node zero? Would the specification
permit bringing out a ground terminal to assign somewhere?
Bob replied that one could connect it to pullup_ref or pulldown_ref.
Walter added that pullup_ref is the more important case. Arpad
asked whether you lose coupling effects if node zero is used. Walter
replied that, yes, this situation should be discouraged. Bob noted
that there is no PDN model in the example.
Michael asked whether we should make this situation illegal. Bob
replied that, if we split pad-to-pin, then the model loses the
reference. The connection becomes undefined. Walter disagreed,
saying it *is* defined. Pin Mapping defines connection of voltages;
the connection is only undefined in the absence of Pin Mapping.
Signal_name connects pin to Pin Mapping. This should not be
forbidden, in his opinion.
In the additional Examples 5 and 6 are full. Example 8 uses
signal_name. Example 9 is buff-pin-pad using data from Example 6
and 8, with signal names rather than direct buffer-to-pin.
Example 10 has a minor error; it should be referring to the “.ts”
extension (the example refers to pulldown_ref). Example 11 has a
PDN, which is allowed. Example 12 is full. Bob took the AR to
correct the errors and send out an updated version. He suggested
that we have to document what Interconnect Model Set means in the
BIRD; the term replaces Interconnect Selector. Michael took the AR
to change Selector to Set in the document and follow appropriate
rules.
Walter replied that there should be no formal rules for sets. We
should just put the rules in a Cookbook document. Bob disagreed,
noting that the industry needs some rules or guidance.
Specifications don’t point to Cookbooks; the Cookbook points to
the specification.
Bob moved to adjourn. Mike seconded. The meeting adjourned.