DATE: 12/13/05
SUBJECT: December 6, 2005 EIA IBIS Open Forum Summit Minutes
VOTING MEMBERS AND 2005 PARTICIPANTS
Actel Prabhu Mohan
Agere (Nirav Patel)
AMD Wasim Ullah
Ansoft Corporation Michael Brenneman, Jack Qiu*, Zhibin Li*
Applied Simulation Technology Norio Matsui
Cadence Design Systems Lance Wang*, [Donald Telian],
Heiko Dudek, Shangli Wu,
Dragoslav Milosevec, Ken Willis,
Lanbing Chen*, Guangli Ju*,
Takada Norikazu*, Haitao Ye*,
Zhangmin Zhong*
Cisco Systems Syed Huq*, Mike LaBonte,
Todd Westerhoff, [Zhiping Yang],
Vinu Armumugham, Salman Jiva,
Satish Pratapneni, Il-young Park,
Sergio Camerlo, Phillipe Sochoux,
Eddie Wu, Gurpreet Hundal,
Jayanthi Natarajan, AbdulRahman Rafiq,
Bill Chen*
Fluent (Chetan Desai)
Freescale Jon Burnett
Green Streak Programs Lynne Green
Hitachi ULSI Systems Kazuyoshi Shoji*
Huawei Technologies Xiangzhong Jiang*, Jin Chen*,
Jun Chen*, Fen Dai*, Zhigao Deng*,
Yuming Du*, Ming Fu*, Jian Hao*, Bo He*,
Zongbin Hong*, Daoxue Hu*, Hongmei Hu*,
Jin Hu*, Peng Hu*, Qinghu Hu*,
Bruce Huang*, Vicky Huang*,
Waneta Huang*, Wengiang Huang*,
Xibin Huang*, Dabin Ji*, Ronghua Jia*,
Jiangyu Jiao*, Honglin Lei*, Auying Li*,
Jinjun Li*, Jun Li*, Qiang Li*,
Shanzhong Li*, Shiying Li*, Zhenhong Li*,
Tracy Liu*, Weidong Liu*, Yong Li*,
Yuping Liu*, Zhongyu Mao*, Kanghua Ou*,
Qingshan Quan*, Amy Tang*, Sheng Tang*,
Stephen Wang*, Xiaodong Wang*,
Zhulin Wei*, HongLiang Yang*,
Qingsong Ye*, Hongcheng Yin*,
Jian Zhang*, Kun Zhang*, Shengli Zhang*,
Hong Zhen*, Yan Zhu*
HiSilicon Technologies Jian Hao*, Leo Hu*
Huawei-3Com Technologies Stephen Cui*, DaoXue Hu*, JianJun Lu*,
Jun Mao*, Bo Wang*, Mingan Xiang*,
Qingxi Zhang*, Wenhua Zhu*
Integrated Circuit Systems (ICS) (Dan Clementi)
Intel Corporation Michael Mirmak*, Arpad Muranyi,
Suresh Chandrasekhar, Bill Gong*,
Kuen Yew Lam*, Fanghu Li*, Dan Liu*,
Fang Lv*, Kitty Ye*, Xinjun Zhang*
LSI Logic Frank Gasparik, William Lau,
Mike Jenkins, Reginald Cowley,
Kusumakumari Matta
Marvell Itzik Peleg
Mentor Graphics John Angulo, Guy de Burgh, Ian Dodd*,
Steven McKinney, Kim Owen,
Stephane Rousseau, Henry Li*, Yan Liu*,
Vivian Pan*, Danny Perng*, Lifu You*,
Tony Zhou*
Micron Technology Randy Wolff, Paul Gregory, Bob Cox
NEC Electronics Corporation Takeshi Watanabe*, Lori Askew,
Takuro Tsujikawa
Panasonic Atsuji Ito*
Samtec [Otto Bennig]
Siemens AG Eckhard Lenski, Katja Koller,
Manfred Maurer, Heinz Ibowski,
Wolfgang Rohmer, Klaus Huebner
Michael Kindij
Siemens Medical David Lieby
Signal Integrity Software [Robert Haller], Douglas Burns,
Barry Katz*, Mike Mayer
Sigrity Sam Chitwood, Jing Ting, Raymond Chen*,
Jiaguan Fang, Teo Yatman,
Michael Leins, Joe Yu*
Silego (Joe Froniewski)
Silicon Image (Ook Kim)
STMicroelectronics Antonio Girardi
Synopsys Warren Wong, Andy Tai, Shulong Wu*
Teraspeed Consulting Group Bob Ross*, Scott McMorrow,
Tom Dagostino
Texas Instruments Otis Gorley
Xilinx Ray Anderson, Sanjay Mehta
Zuken Michael Schaeder, Ralf Bruening,
Patrick Fang*, Hongrun Li*
OTHER PARTICIPANTS IN 2005:
Altera Khalid Ansari
Apple Computer Zhiping Yang*
Bayside Design Kevin Roselle
Beijing Peking University Chunfeng Li*, Jianhua Liang*,
Jinglin Lua*, Shengyong Peng*,
Jing Sun*
CelsioniX Kellee Crisafulli
China Integrated Circuits Liyoung Ding*
Dell Aubrey Sparkman
EDN China Tracy Tang*
EE Times China Laker Pu*, Melody Zhao*
(Global Sources and CMP)
EMC Brian Arsenault, Daniel Nilsson,
Jason Pritchard, Jinhua Chen
Enterasys Networks [Fabrizio Zanella]
EPFL Alain Vachoux
Fiberhome Telecommunications Qian Liao*, Wao Tang*, WenWei Xiao*,
Technologies Qi Zheng*
Foxconn Technology Group Eric Lee*, Scott Lin*, Fred Ou*,
Fred Qi*, Kevin Wang*, Jason Zhang*
Fujitsu Siemens Computers Martin Ramme
GEIA (Chris Denham)
Global Engineering Solutions Zen Liao*
Infineon Technologies AG Thomas Steinecke, Minea Gospodinova,
Amir Motamedi, Yann Zinsius,
Christian Sporrer, Radovan Vuletic
INSA Toulouse Etienne Sicard
JEITA Toshiro Honda*
JMD International Joe Socha
KAW/Japan Kazuhiko Kusunoki*
Lenovo Wei Kang*, Wenxin Lin*
Leventhal Design Roy Leventhal
Lynguent Andrew Levy
NetLogic Eric Hsu
Nokia Erno Lahteenmati, Tapani von Rauner
North Carolina State Univ. Ambrish Varma
Politecnio di Torino Igor Stievano
QDI Fang Yang*, Fen Yang*
Shenzhen Bureau of Science, Jian Lu*
Technology & Information
Si2 Sumit DasGupta
Silicon Bandwidth [Kim Helliwell]
Sun Microsystems Gustavo Blando
Tandem Consulting Jack Luo*
Time Domain Analysis Systems Dima Smolyansky, Steve Corey
Toshiba Yasmasa Kondo*
UTStarcom Telecom Co. Xiangao Wei*, FengXue Ying*,
Dingziang Zhou*
Western Digital Mohammad Ali
ZTE Corporation Yunhang Gao*, Yunhang Gao*,
Chunmei Huang*, Huiqiang Jing*,
Kang Li*, YongFeng Li*, Chunjie Liu*,
Jian Peng, Lin Na Shuang*,
Shiju Sui*, Jiuzhou Tang*,
Xinghai Tang*, Changjun Wang*,
Daguo Wang*, Xianmei Wang*,
Leijia Xiong, Xuequan Yu*,
Chengjun Zhang*, Hailong Zhang*,
Ivan Zhang*, Lu Zhang*, Shunlin Zhu*
Independent Bernhard Unger (Siemens retired),
Kim Helliwell
Unknown Xiaoyun Bao*, Caltong Luo*
In the list above, attendees at the meeting are indicated by *.
Principal members or other active members who have not attended are in
parentheses. Participants who no longer are in the organization are in
square brackets.
UPCOMING MEETINGS
The bridge numbers for future IBIS teleconferences are as follows:
Date Telephone Number Bridge # Passcode
December 16, 2005 1-916-356-2663 4 574-7106
All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas
are typically distributed seven days before each Open Forum. Minutes
are typically distributed within seven days of the corresponding
meeting. When calling into the meeting, provide the bridge number and
passcode at the automated prompts. If asked by an operator, please
request to join the IBIS Open Forum hosted by Michael Mirmak.
For international dial-in numbers, please contact Michael Mirmak.
NOTE: "AR" = Action Required.
--------------------------------MINUTES-----------------------------------
INTRODUCTIONS AND MEETING QUORUM
The Asian IBIS Summit was held in Shenzhen, China at the Crowne Plaza
Hotel Shenzhen. We list 154 people who participated representing over 30
organizations, although the actual attendance was probably larger. Most
participants were from China while several more people came from the
United States, Japan and Malaysia.
Huawei Technologies served as the primary sponsor with Cadence Design
Systems, Mentor Graphics Corporation, Signal Integrity Software (SiSoft)
and Sigrity serving as co-sponsors to provide outstanding meeting
facilities and arrangements. Tables for four EDA vendor co-sponsors were
positioned outside the room in the registration and refreshment area.
The speakers optionally delivered their presentations in English or
Chinese. Most presenters including several US based speakers chose
Chinese. Either the speakers or Lance Wang (in most cases) provided
extended summaries and review in the second language to convey the
content more clearly. The questions and discussion were handled in a
similar bi-lingual manner.
XiangZhong Jiang from the primary sponsor, Huawei Technologies, opened
the Asian IBIS Summit by welcoming the participants, thanking the
co-sponsors and expressing enthusiasm for the meeting. Michael Mirmak
also welcomed everyone and noted the strong support in Asia from
China and JEITA in Japan. He hoped the information would be useful
in dealing with the ever increasing signal integrity challenges and
corresponding IBIS modeling behavioral methods.
Michael then introduced Dr. Jian Lu, Deputy Director-General of the
Shenzhen Bureau of Science, Technology and Information. Dr. Lu noted
increasing need for advanced integrated circuit based technologies. On
behalf of his Bureau, he thanked the sponsors and welcomed the
participants to promote better technological advances for China and the
world community.
The latest versions of the presentations and a copy of the Conference
Record will be uploaded under
http://www.eda.org/pub/ibis/summits/dec05/
PRESENTATIONS
The remainder of the minutes briefly summarize some of the points in
the presentations. Additional information is available in the uploaded
documents.
Some standard abbreviations are used in the minutes including:
Decap Decoupling capacitor
ECL Emitter coupled logic
EMI Electromagnetic interference
EMC Electromagnetic compliance
JEITA - WG
Japanese Electronics and Information Technology Industries
Association - Working Group
PCB Printed circuit board
PDS Power delivery system
PI Power integrity
PRBS Pseudo random bit sequence
SI Signal integrity
SSN Simultaneous switching noise
SSO Simultaneous switching output
Some others are assumed to be well-known such as AC, DC, DDR, DDR2, Spice,
IBIS, VHDL-AMS, I/O, etc., or are defined below.
IBIS AND BEHAVIORAL MODELING CHALLENGES
Michael Mirmak (Intel Corporation, USA)
Michael Mirmak introduced the primary concepts of IBIS tables and structure.
IBIS is one type of behavioral model, but other types include ICM (IBIS
Interconnect Modeling Specification), IMIC (I/O Model for Integrated
Circuits), ICEM (Integrated Circuit Electrical Model), VHDL-AMS, and
Verilog-AMS. These models are used to replace the internal buffer design
information with observations of the electrical ports or terminals. Michael
listed advantages of behavioral methods and showed that IBIS works well
when compared with SPICE. Behavioral modeling methods are needed in the
future, because increased speed (processor MIPS) and buffer transistor
complexity tend to track.
IBIS is expanding with connections to other behavioral technologies to
address the analysis needs related to buffer complexity and the growing
processing power.
Michael listed some IBIS reference information and links and welcomed
worldwide participation in IBIS.
FIBERHOME TELECOMMUNICATIONS TECHNOLOGY EXPERIENCES WITH IBIS MODELS
Qi Zheng (Fiberhome Telecommunications Technology, China)
Qi Zheng shared some of Fiberhome's experiences. IBIS is needed for
checking waveform quality and flight time calculations. Some basic
Version 2.1 parameters are mostly used, versus Version 3.2 or 4.0
parameters. Some problems are encountered, but success stories exist
for multi-drop bus analysis and timing analysis. However, Qi listed some
quality, driver strength and timing issues.
Fiberhome is expecting continued interaction between tool vendors, model
makers, other tools and the end user to address the problems in high
speed, serial interconnection analysis.
THREE FACETS OF IBIS: INTERFACE, BEHAVIOR AND MEASUREMENT
Ian Dodd* and Henry Li** (Mentor Graphics Corporation, *USA and **China)
Ian Dodd listed some objectives of SI engineers to maximize performance,
ensure reliable operation and minimize per unit costs. These objectives
are met by investing in accurate timing and SI analysis to control safety
margins in the signal path.
Ian highlighted top-level IBIS Version 3.2 items related to the basic
timing and clock skew problem. He recommended some measurement
enhancements needed for analysis.
Henry Li followed Ian by showing the wrapper structure for an IBIS Version
4.1 model to provide the framework for some advanced multi-lingual linkages
and analysis. The wrapper structure functions as the traditional IBIS
model framework in analysis tools.
SIMULATION WITH IBIS IN TIGHT TIMING BUDGET SYSTEMS
Shiju Sui, (ZTE Corporation, China)
Shiju Sui focused on applying IBIS in timing budget analysis. She
introduced common-clock synchronous timing analysis and loose timing
budget system analysis. Its required inputs are timing topology,
component-level timing data, operating clock frequency, and approximated
flight time and guard band.
Tight timing budget system analysis also has required inputs of timing
topology, component-level timing data, and operating clock frequency.
Also, simulation with component models is mandatory, and more advanced
numerical processing is needed. IBIS models are useful for this.
Propagation delay is the sum of T-line delays in the path. Flight time is
the time it takes the data sent from the driver to settle at the
receiver's input. Shiju showed that simulation result waveforms need to
be carefully analyzed for proper interpretation. Both the component data
sheet and IBIS model should be checked. Avoid double counting of C_comp
and load. Be careful with receiver thresholds. Specifically, the data
sheet and timing test load should agree for proper measurement
interpretations. To avoid double counting of C_comp and load, one should do
the compensation from simulated flight time and subtract their effect from
Tco. Negative flight time can occur for short paths or when the test load
Tco measurement is heavier than the actual load. Corners should be
included in the analysis.
Shiju discussed several ways to specify receiver thresholds though the
[Receiver Thresholds] sub-parameters in IBIS Version 4.0. Even with
thresholds, some margins are needed (guard band time) to account for
effects such as SSO, crosstalk, inter-symbol interference and power
supply noise.
With complex topologies, component path delays are added and timing
margins decrease. Alternate timing methods can be used including
worst case timing, statistical timing, and Monte Carlo timing analysis.
JEITA EDA - WG ACTIVITY AND STUDY OF INTERCONNECT MODEL
Takashi Watanabe (NEC Electronics Corporation, Japan)
Takashi Watanabe started with a JEITA EDA - WG overview and described how
their EDA model focuses on consumer electronics and, possibly in the future,
automobile electronics. IBIS Version 4.1 is applicable. The main issues
are EMI, SI, and PI. Takashi explained this in terms of active components
ranging from discrete devices to LSI devices and passive cables,
connectors, crystal oscillators, flexible PCBs, etc.
The JEITA EDA - WG consists of sixteen major companies. The short term
direction is to study the interconnect model and also passive components.
The group is developing an IBIS home page and is discussing a case
study of simulation for digital consumer electronics.
Takashi shared the outline of the interconnect study from signal generator
connectors, cable to another connector and terminators for target
applications such as InfiniBand, RapidIO, DDR and PCI-Express.
He also shared the JEITA IBIS Model Portal site plan showing a kitchen
analogy containing an IBIS Cookbook, libraries, verification tools, IBIS
models, instruction manuals, EMI and SI simulation and even a garbage
can for bad IBIS models. He also showed and IBISIndicator(tm) utility
by KAW/Japan with a racing car dashboard interface for performance
monitoring.
LUNCH
The meeting adjourned for a buffet lunch served to all the participants.
The IBIS officers and representatives of the sponsoring companies met
separately with four representatives of the Chinese technical press from
EDN China, EE Times China and China Integrated Circuit.
IBIS AND POWER DELIVERY SYSTEMS
Xiangzhong Jiang, Jinjun Li, and Shengli Zhang (Huawei Technologies, China)
Jinjun Li described the IBIS history from the time that the SI department
was founded in 1999. A modeling group was formed in 2001. The model
platform supports IBIS models, SPICE models and capacitance and inductance
modeling.
The IBIS validation process involves using ibischk3 for detecting a number
of errors and warnings. Jinjun discussed some inspection details and
listed some simulation checks.
SPICE models are used to model a ceramic capacitor consisting of stacked
plates. This is modeled by a set of capacitor-resistor sections connected
by inductors. Jinjun compared measurement and simulation results for
several capacitors.
The power integrity platform uses S-parameters for interconnects. Jinjun
illustrated this with some simulation and overlaying measurement results
for a sample net.
Jinjun concluded by stating that Huawei has a validated IBIS library along
with a SPICE model library of passive components. Huawei has been
starting power integrity simulations and has found that the simulated and
measured impedances are consistent and useful for addressing noise issues.
POWER DELIVERY SYSTEM, SIGNAL RETURN PATH AND SSO ANALYSIS GUIDELINES
Raymond Y. Chen and Sam Chitwood (Sigrity, USA)
Raymond Chen focused on a design flow where signal and power integrity
analysis are performed at each stage - pre-layout SI analysis, post-layout
SI analysis and design evaluation.
For Stage 1, Raymond listed guidelines for PDS design, signal return, SSO
and EMI early prevention. For Stage 2, he listed PDS design checks, SSO
simulation, decap optimization and model generation. For Stage 3, he
listed options for PDS structure, signal return path, SSO and EMI for the
purpose of re-spinning the design.
Raymond then presented several simulations showing the effect of decap
placement for delta-I noise, power/ground impedance extraction, and
optimizing decap selection. He described how PDS optimization involved IR
drop analysis and the importance of return path effects and SSN effects on
the receiver.
Raymond listed several reasons why S-parameters are important for SSO
analysis. The simpler approaches miss important details. He suggested
extracting only the nets of interest and setting the appropriate
frequency range (including low frequency data). Stuck bits and PRBS
provide useful methodologies for SSO.
SPLITTING THE C_COMP FOR POWER INTEGRITY SIMULATIONS
Zhiping Yang (Apple Computer, USA)
Zhiping Yang listed several reasons why the split ratio C_comp could impact
PI simulations including how it provides an effective local decoupling
capacitance, and also on noise and dynamic current distribution. He then
showed briefly some model topologies and theoretical derivations for
driving the I/O pin impedance.
After illustrating some state dependency (low state, high state) on
impedances and various capacitances and resistances versus frequency,
Zhiping drew the following conclusions:
C_comp is frequency and state dependent
C_comp ratio is also frequency and state dependent
C_comp and its split ratio are important for PI simulations
The existing C_comp and I-V table data may not be complete, even at
steady state
USING IBIS FOR SI ANALYSIS
Lance Wang* and Zhangmin Zhong** (Cadence Design Systems, *USA and **China)
Lance Wang showed the behavioral basis and structure of IBIS. The
behavioral methodology expanded from IBIS Version 1.1, 2.1, 3.2 and,
currently, 4.1 to address technological advances. However, more models for
complex IO structures are falling outside the IBIS Version 4.1 box. While
SPICE support of IBIS is solid with semiconductor and EDA vendors, SPICE
tools are also providing IBIS support.
Zhangmin Zhong showed examples demonstrating the advantages of IBIS. The
results are accurate, and simulation times are significantly shorter.
IBIS also protects the intellectual property. Zhangmin showed simulation
for 133 MHz and 622 Mbps cases.
Lance Wang then discussed advanced IBIS technologies seen in complex IOs.
For example, pre-emphasis/de-emphasis formed by a one bit delayed and
inverted in the emphasis buffer. Another complex IO includes a self
calibrating structure for selecting the buffer output impedance. Other
advanced technologies are included. Lance concluded that macromodeling is
a methodology. Architecture templates provide the basis for macromodel
construction. Lance showed excellent correlation with an Altera Stratix
GX buffer SPICE and macromodel simulation. For a selected template, the
model construction is based on iterative fitting of a small set of
parameters. This can be packaged in design kits.
MACRO MODEL AND MULTI-GHZ SYSTEM SIMULATION
Shunlin Zhu, (ZTE Corporation, China)
Shunlin Zhu listed the features of SPICE models, IBIS models and
macromodels. He stated that the macromodel methodology can be quite
involved and gave several reasons based on the fact that different
problems require different approaches.
Complex IOs can be modeled using IBIS multi-lingual modeling (VHDL-AMS,
Verilog-AMS, SPICE subcircuits, with External Models and with
S-parameters). Macromodeling is done by combining SPICE subcircuits with
behavioral models.
The macromodeling flow is bottom-to-top, where the macromodel is formed
from an IBIS model base and then correlated with SPICE simulation. Shunlin
illustrated macromodeling using a SERDES device with pre-emphasis. The IBIS
data could be placed in the macromodel template along with some additional
parameters.
Shunlin presented excellent correlation between simulation with macromodels
and measurement for several pre-emphasis settings. He also compared
measurement and simulation for a Multi-GHz system interconnect simulation.
Along with the transceiver and its package model, the interconnect (traces,
vias, and connectors) needs to be modeled. Data is extracted from a 2D/3D
EM solver and correlated based on VNA and TDR/TDT measurements. SI/PI/EMC
simulations are performed. The eye diagram and design margin budget is
checked. The results are then optimized. Shunlin showed some eye diagrams
for selecting the best pre-emphasis setting. These correlated well with
measurements.
IBIS MODEL FOR DDR2 ANALYSIS
Barry Katz (Signal Integrity Software (SiSoft), USA)
Barry Katz gave a brief DDR overview and then listed DDR2 enhancements.
One is to use selected resistances for on-die termination (ODT) in the
receiving mode only. Barry showed how these are configured. While
SPICE provides slow but accurate simulations, IBIS models can be used
in place of SPICE models with matching results. IBIS models have the
advantage of being portable among several simulators.
Barry listed several methods in IBIS to add ODT. One method is to use the
[Submodel] keyword for modal-based (receiver only) selection. A separate
receiver model could be added, but switching in models increases the
analysis complexity. The third option is to use the existing four I-V
table IBIS structure, and add the ODT structure in the clamp tables, but
subtract those additional currents from the [Pullup] and [Pulldown]
tables. This process creates non-monotonic [Pullup] and [Pulldown]
tables, but it produces acceptable results. Barry showed how Thevenin
ODT can be modeled using the two clamp tables. While the process
involves allocating currents to various tables, the total currents from
adding the tables appropriately is the same as the extracted currents.
For future consideration in IBIS, Barry recommends slew rate de-rating
tables. Straight line waveform approximations can be used for de-rating.
PRACTICAL MEASUREMENT VS. SIMULATION CORRELATION WITH DDR2-667 INTERFACE
Kazuyoshi Shoji (Hitachi ULSI Systems Co., Japan)
Kazuyoshi Shoji indicated that people question whether IBIS can be used
over SPICE. To address this, he outlined an experiment based on a real
design to compare SPICE simulation, IBIS simulation and measurements. The
circuit consisted of a DRAM connected to an ASIC though PCB transmission
lines. The IBIS simulation correlated well and was four times faster than
SPICE simulation for the DDR2-667 test case.
With good FOM (figure of merit) correlation above 96%, and faster
simulations, Kazuyoshi concluded that IBIS model simulation is fairly
accurate and fast - a good choice for practical purposes.
IMPROVING IBIS ECL ALGORITHMS
Bob Ross (Teraspeed Consulting Group, USA)
Bob Ross briefly presented the mathematical basis of the 2-waveform
algorithm. Variations of this algorithm are used in most EDA tools. The
process involves extracting from waveform information the Ku(t) and Kd(t)
multipliers for the [Pulldown] and [Pullup] tables. These multipliers are
used to form the IBIS simulation model. Bob showed that this approach
yields good results with overlaying comparisons between source and
simulation waveforms.
The ECL I-V data is shaped differently from the traditional CMOS based
I-V table data. The existing algorithm has been applied to this data
in several EDA tools. However, some problems exist under certain load
conditions. The approach based on I(V) tables has a region under a
simplified test case where the [Pulldown] currents are zero, and the
2-waveform approach has no solution. This can be resolved by recasting
the tables as V(I) tables using and deriving a different Mu(t) and Md(t)
multipliers.
While this is not a high priority problem in industry, the main point for
presenting this is to point out that with existing tools and with more
advanced methods such as with programmable multi-lingual extensions or
macromodel additions, the modeler still needs to pay attention to the
underlying algorithm and equation details.
CONCLUDING REMARKS
Michael Mirmak thanked the presenters and the co-sponsors for the
exceptionally high quality meeting, high quality presentations and strong
support. He looked forward to future IBIS Summits in Asia.
Xiangzhong Jiang provided a final thank you and closed the meeting.
After the meeting adjourned, all the participants completed feedback forms
and received a high quality cloth laptop or brief case bag to commemorate
the event. It listed the event and contained the logos of IBIS and the
sponsors.
NEXT MEETING
The next IBIS Open Forum teleconference will be held December 16, 2005 from
8:00 AM to 10:00 AM US Pacific Time.
============================================================================
NOTES
IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046
michael.mirmak@intel.com
Senior Analog Engineer, Intel Corporation
FM6-45
1900 Prairie City Rd.
Folsom, CA 95630
VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475
rrwolff@micron.com
Simulation Engineer, Micron Technology, Inc.
8000 S. Federal Way
Mail Stop: 01-711
Boise, ID 83707-0006
LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363
lwang@cadence.com
Senior Member, Technical Staff, Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA 01824
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400
bob@teraspeed.com
Staff Scientist, Teraspeed Consulting Group
10238 SW Lancaster Road
Portland, OR 97219
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