DATE: 09/28/05
SUBJECT: September 19, 2005 EIA IBIS Open Forum Summit Minutes
VOTING MEMBERS AND 2005 PARTICIPANTS
Actel Prabhu Mohan
Agere (Nirav Patel)
AMD Wasim Ullah
Ansoft Corporation Michael Brenneman
Applied Simulation Technology Norio Matsui
Cadence Design Systems Lance Wang*, [Donald Telian],
Heiko Dudek, Shangli Wu*,
Dragoslav Milosevec, Ken Willis*
Cisco Systems Syed Huq, Mike LaBonte*,
Todd Westerhoff*, Zhiping Yang,
Vinu Armumugham,
Salman Jiva, Satish Pratapneni,
Il-young Park, Sergio Camerlo,
Phillipe Sochoux, Eddie Wu,
Gurpreet Hundal, Jayanthi Natarajan
AbdulRahman Rafiq
Fluent (Chetan Desai)
Green Streak Programs Lynne Green
Hitachi ULSI Systems Kazuyoshi Shoji*
Huawei (Jiang Xiang Zhong)
Integrated Circuit Systems (ICS) (Dan Clementi)
Intel Corporation Michael Mirmak*, Arpad Muranyi*,
Suresh Chandrasekhar
LSI Logic Frank Gasparik, William Lau,
Mike Jenkins, Reginald Cowley,
Kusumakumari Matta
Marvell Itzik Peleg
Mentor Graphics John Angulo, Guy de Burgh, Ian Dodd,
Steven McKinney, Kim Owen,
Stephane Rousseau
Micron Technology Randy Wolff*, Paul Gregory, Bob Cox*
NEC Electronics Corporation Takeshi Watanabe, Lori Askew,
Takuro Tsujikawa
Panasonic Atsuji Ito
Samtec [Otto Bennig]
Siemens AG Eckhard Lenski*, Katja Koller,
Manfred Maurer, Heinz Ibowski,
Wolfgang Rohmer, Klaus Huebner
Michael Kindij
Siemens Medical David Lieby
Signal Integrity Software Robert Haller*, Douglas Burns,
Barry Katz, Mike Mayer
Sigrity Sam Chitwood, Jing Ting, Raymond Chen
Jiaguan Fang, Teo Yatman, Michael Leins
Silego (Joe Froniewski)
Silicon Image (Ook Kim)
Synopsys Warren Wong, Andy Tai
Teraspeed Consulting Group Bob Ross*, Scott McMorrow,
Tom Dagostino*
Texas Instruments (Steve Spencer), Otis Gorley
Xilinx Ray Anderson, Sanjay Mehta
Zuken Michael Schaeder, Ralf Bruening
OTHER PARTICIPANTS IN 2005:
Altera Khalid Ansari
Bayside Design Kevin Roselle
CelsioniX Kellee Crisafulli
Dell Aubrey Sparkman
EMC Brian Arsenault*, Daniel Nilsson,
Jason Pritchard, Jinhua Chen
Enterasys Networks Fabrizio Zanella
EPFL Alain Vachoux
Freescale Jon Burnett
Fujitsu Siemens Computers Martin Ramme
GEIA (Chris Denham)
Infineon Technologies AG Thomas Steinecke, Minea Gospodinova,
Amir Motamedi, Yann Zinsius,
Christian Sporrer, Radovan Vuletic
INSA Toulouse Etienne Sicard
JMD International Joe Socha
KAW Kazuhiko Kusunoki
Leventhal Design Roy Leventhal
Lynguent Andrew Levy
NetLogic Eric Hsu
Nokia Erno Lahteenmati, Tapani von Rauner
North Carolina State Univ. Ambrish Varma
Politecnio di Torino Igor Stievano
Si2 Sumit DasGupta
Silicon Bandwidth [Kim Helliwell]
STMicroelectronics Antonio Girardi
Sun Microsystems Gustavo Blando
Time Domain Analysis Systems Dima Smolyansky, Steve Corey
Western Digital Mohammad Ali
Independent Bernhard Unger (Siemens retired),
Kim Helliwell
In the list above, attendees at the meeting are indicated by *.
Principal members or other active members who have not attended are in
parentheses. Participants who no longer are in the organization are in
square brackets.
UPCOMING MEETINGS
The bridge numbers for future IBIS teleconferences are as follows:
Date Telephone Number Bridge # Passcode
October 7, 2005 1-916-356-2663 2 431-4165
All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas
are typically distributed seven days before each Open Forum. Minutes
are typically distributed within seven days of the corresponding
meeting. When calling into the meeting, provide the bridge number and
passcode at the automated prompts. If asked by an operator, please
request to join the IBIS Open Forum hosted by Michael Mirmak.
For international dial-in numbers, please contact Michael Mirmak.
NOTE: "AR" = Action Required.
--------------------------------MINUTES-----------------------------------
INTRODUCTIONS AND MEETING QUORUM
Michael Mirmak opened the meeting by thanking the co-sponsors: Cadence
Design Systems, Intel -- for providing teleconference support -- Mentor
Graphics, and SiSoft (Signal Integrity Software). Michael particularly
thanked Robert Haller of SiSoft for his "on site" assistance with summit
logistics and booth setup. Michael also recognized the long-standing
co-sponsorship relationship of IBIS and the IEC in hosting IBIS Summits
at DesignCon events.
Michael called for individual introductions of the participants. Fifteen
people were in attendance, including five over the teleconference line.
A cross-section of IBIS users, IBIS model makers and EDA tool vendors
were represented.
IBIS CHAIR'S REPORT AND ROADMAP UPDATE
Michael Mirmak, Intel Corp.
Michael Mirmak presented a summary of the most recent events relating to
both the IBIS specification and the Open Forum as an organization. ICM
1.1 has been submitted for EIA balloting and has unofficially passed,
based on the latest data from the GEIA. IBIS 3.2 reballoting through
the EIA has been officially completed. Further, the IBIS Modeling
Cookbook for Version 4.0 was released on September 16.
Michael reminded the participants that, in addition to IBISCHK4, a
"private code" parser release of ICMCHK1 is now available for purchase.
Several BIRDs are up for consideration, including the latest version
of BIRD95 (Power Analysis using IBIS), plus BIRD97/98 (Gate Modulation
Effect). In addition, a draft BIRD100 for linking IBIS to ICM is
under development through the Futures Task Group.
Participants asked several questions regarding Futures work. First,
some noted that a combination of the [External Circuit] and the
[Model] keywords would be useful for several applications. Michael
responded that this had been proposed earlier and was still under
consideration. Participants also inquired whether BIRD100 was available
on-line. Michael noted that it was, through the Futures Task Group.
VERSION 3.2 EXPERIENCE MODELING FAST, TWO-TAP PRE-EMPHASIS BUFFER
Bob Ross, Teraspeed Consulting Group
Bob Ross summarized issues he experienced while attempting to create a
differential pre-emphasis IBIS model from SPICE circuit data. Major issues
were encountered in correlation, particularly due to differences between the
TX+ and TX- "halves" of the buffer plus C_comp adjustment difficulties.
However, creative use of IBIS keywords and use of a variety of tools
eliminated most of these issues.
One of Bob's customers had stated that multi-tap pre-emphasis "could not be
done in IBIS" for the ASIC differential buffer needed. However, encrypted
HSPICE was problematic for customers, and business issues prevented the use
of 3-way NDAs. Bob showed that an IBIS model with reasonable correlation
accuracy could be produced for solution space exploration.
A participant inquired whether the SPICE extraction for the model data was
done by hand. Bob responded that a SPICE2IBIS-like process was used. A
follow up question was asked: were all the models from the same vendor?
Bob responded yes, all the models were from the same vendor and were
organized with the "top-level" visible and subcircuits encrypted.
IBIS 4.1 MACROMODEL LIBRARY FOR SIMULATOR INDEPENDENT MODELING
Todd Westerhoff, Cisco Systems
Todd Westerhoff provided an overview of the Macromodeling Task Group's
direction and recent efforts. The industry recognizes the increasing
difficulty in using IBIS to model the newest interface technologies,
and has witnessed an increase in SPICE usage. The IBIS 4.1 AMS extensions
do not yet have widespread support, but no standard SPICE exists either.
Cadence's Macromodeling proposal has merit, but was perceived as an AMS
competitor. The Macromodeling library approach models a universal set of
primitives, so that non-AMS-supporting tools can substitute SPICE circuit
information for AMS language syntax.
Todd outlined the current primitive definitions and some issues being found
in the languages used. At this point, literals cannot be passed into
functions for use as executable code under Verilog-AMS. Arpad Muranyi noted
that the team chose Verilog-A as a starting language due to its universality
and resemblance to SPICE, but the team is seeing limitations in it now.
Issues concerning Verilog-A only apply to "pure" Verilog-A simulation tools;
most tools implement Verilog-AMS or some variant in addition to -A. Other
code could be used in place of Verilog-A, where native tool functions are
helpful.
Lance Wang asked about the building block library; how does it work? Todd
responded that tools would instantiate building blocks and pass in
parameters. All vendors would use the library, with a "fixed set of
building blocks." A 1-1 mapping between elements of common SPICE and the
library was not assumed.
EXTRACTING ON-DIE TERMINATORS
Bob Ross, Teraspeed Consulting Group
Bob Ross reviewed a detailed set of proposed procedures for creating IBIS
models for designs where internal or on-die terminations existed. Bob noted
that previous procedures and documents suggested "clip and extend" as a
suitable method; this may introduce distortions into simulations for power
supply variation. Bob instead suggested an extrapolation-based method he
called "Deviate Extrapolate Calculate." In this method, I-V table deviation
from an ideal resistor is determined and assigned proportionally as
deviations from ideal "pullup" and "pulldown" on-die termination resistors
to produce the corresponding [POWER Clamp] and [GND Clamp] tables. The
clamps would therefore avoid double-counting of diode effects. The
remaining table data would them be extrapolated and the final clamp table
data calculated and used. Arpad Muranyi asked about "calculate" versus
"extrapolate" - what is the difference? Bob Ross responded that "calculate"
involves subtracting the extrapolated value on the "right side" of the I-V
curve chart from the total I-V chart behavior on the right side of the
chart.
One participant asked how a model author can determine the buffer's internal
structure when the buffer is essentially a "black box." Bob Ross
responded that the most simple structure is assumed for IBIS modeling
purposes. An "override structure might be selected based on some additional
structural information that might be available from the vendor or possibly
deduced from additional testing of the buffer by varying the supply voltage.
IBIS PARSER BUG90 AD-HOC PRESENTATION
Robert Haller, Signal Integrity Software
Bob Haller presented a recent BUG filing against the IBIS parser as an
example of a proposed new type of warning message. BUG90 identifies that
the parser accepts without comment Vmeas values not between Vih and Vil.
While not fatal to model performance, this could be serious enough to
distort simulation output.
Bob Haller expanded on this to propose creating "Caution" flags, in addition
to the current "Error" and "Warning" types already in the parser. Bob
concluded by listing a set of parser improvements already identified by the
Quality Task Group.
Michael Mirmak noted three points. 1) The committee agreed to create and
prioritize a list of checks they felt were missing. A formal parser
specification detailing what the parser checks and how it does so would make
future improvements easier, but it is not in the Quality subcommittee's
charter or goals. 2) He asked about the difference between Cautions and
Warnings. 3) He advised caution regarding introducing quality flags into
the parser, else we force interpretations on tool vendors.
Bob Haller responded by explaining that these levels corresponded to:
Error - absolutely wrong
Warning - may possibly not be a problem, but usually is a problem
Caution - usually not a problem, but may be in this case
Bob also noted that Quality checks are already done by tools anyway. Why
shouldn't we make them part of the parser's standard set of checks? Bob
also suggested making the checks flexible, perhaps using switches at the
command line. In general, he advised that the IBIS community not become
complacent about IBISCHK warnings showing up, citing the frequent reports
of non-monotonicity in previous parsers. Should we deprecate non-monotonic
Warnings to Cautions?
IBIS "OVER CLOCKING" CASE
Robert Haller, Signal Integrity Software
Bob Haller showed the simulation impact of IBIS models with large amounts of
V-T table "dead time," making the V-t table duration similar to the pulse
width of the interface. With a V-t table where the edge transition is
sharp compared to the table duration, results are predictable, if the
duration is shorter than the pulse width. Once the edge transition
is comparable to the duration, cycles appear to be dropped. Shifting the
corners in relation to each other can assure V-t completion within the
pulse width. This of course comes at the cost of corner-to-corner time
correlation; no requirement for this exists in the specification.
Michael Mirmak commented that time-miscorrelation of edges can result in
errors when corner-to-corner comparisons are used to determine the effects
of PVT on relative Tco. Arpad Muranyi suggested that further editing of the
V-t tables could be performed in the specific examples cited to improve
correlation.
ASIAN IBIS SUMMIT UPDATE
Bob Ross, Teraspeed Consulting Group
Bob updated the team on the status of the IBIS Summit for Asia, scheduled
for Tuesday, December 6 at the Crowne Plaza Hotel in Shenzhen, People's
Republic of China. Six sponsors are currently scheduled: Huawei
Technologies, Cadence Design Systems, Mentor Graphics, Sigrity, SiSoft, and
Zuken. Vendor tables will be permitted outside the main venue, but open
IBIS Summit rules will apply for the main agenda. At present, at least nine
presentations were anticipated, with an emphasis on IBIS applications and
general background, as opposed to issues of controversy.
Bob noted that representatives of JEITA will be present and will likely
deliver a brief talk. At least two new Chinese presentations are scheduled,
with more likely. In short, the focus is on what the presenters can give
attendees that they can use immediately and can implement soon in their
tools.
Arpad Muranyi asked whether the IBIS board can survey prospective
participants to determine their experience level and interest. Bob agreed
and proposed to have pre-posting review and feedback before the materials
are sent to the printer.
Lance Wang echoed Bob's earlier statements, noting that many people in China
need assurances about IBIS accuracy and basic education about IBIS. In
particular, Chinese users need information on serdes and other new
technologies, plus basic information on running signal integrity
simulations.
Some discussion ensued regarding language and translation. Bob Ross noted
that the main language would be English, and the presentation slides should
be in English. If a presenter feels more comfortable delivering the
presentation in Chinese, he or she can do so. In all cases an alternate
language summary is expected at the end, either by Lance Wang or by the
presenter or other company staff. Also, if possible, the authors might
want to annotate the English-based slides with Chinese text for clarity.
NEW TECHNICAL ISSUES AND AD-HOC DISCUSSION
Michael Mirmak opened the floor for general discussion. Conversation
first turned to BUG90 and a parser specification. Michael again noted
that no formal document exists giving the entire specification for the
parser. Bob Ross added that documentation for the algorithms does not
exist either, which has caused issues in the past (for example, the
voltage step size minimum at 1e-15 was not known until a BUG report
revealed it).
Mike LaBonte suggested running a capture program, to execute a line-by-line
string search of all the warnings and errors, based on checking runs.
Michael suggested that this would not be necessary, so long as Quality
committee reviewers with access rights to the source code could review
the output messages.
Bob Haller suggested that the IBIS Quality Task Group can talk to vendors
on the cautions issues. Bob reiterated the classification scheme: Error is
never right, Warning is wrong in most cases, Caution is speculatively wrong.
The Quality Task Group will document the list of checks that are missing.
Regarding the terminator presentation from Bob Ross, Arpad Muranyi noted
that the terminator curve shape is essentially arbitrary if the device is
non-linear. He asked how Bob Ross derived the equation fit. Bob agreed
that an infinite number of solutions exists for such cases; he selected the
most simple solution to fit the results. Arpad expressed some concern about
arbitrary selection of termination values, noting that Vcc-relative tables
were used in IBIS because tools could not extract the correct currents out
of the correct rails when parasitics were added.
At the conclusion of the ad-hoc discussion, Michael adjourned the meeting.
NEXT MEETING
The next IBIS Open Forum teleconference will be held October 7, 2005 from
8:00 AM to 10:00 AM US Pacific Time. A vote is scheduled for BIRD95.6.
============================================================================
NOTES
IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046
michael.mirmak@intel.com
Senior Analog Engineer, Intel Corporation
FM6-45
1900 Prairie City Rd.
Folsom, CA 95630
VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475
rrwolff@micron.com
Simulation Engineer, Micron Technology, Inc.
8000 S. Federal Way
Mail Stop: 1-711
Boise, ID 83707-0006
LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363
lwang@cadence.com
Senior Member, Technical Staff, Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA 01824
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400
bob@teraspeed.com
Staff Scientist, Teraspeed Consulting Group
10238 SW Lancaster Road
Portland, OR 97219
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