DATE: 02/07/05
SUBJECT: January 31, 2005 EIA IBIS Open Forum Summit Minutes
VOTING MEMBERS AND 2005 PARTICIPANTS
Actel (Prabhu Mohan)
Agere (Nirav Patel)
AMD (Wasim Ullah)
Ansoft Corporation Michael Brenneman*
Applied Simulation Technology Norio Matsui*
Cadence Design Systems Lance Wang*, Donald Telian*
Cisco Systems Syed Huq*, Mike LaBonte, Todd Westerhoff*,
Zhiping Yang*, Vinu Armumugham*,
Salman Jiva*, Satish Pratapneni*,
Il-young Park*, Sergio Camerlo*,
Phillipe Sochoux*, Eddie Wu*,
Gurpreet Hundal*, Jayanthi Natarajan*
Freescale (Jon Burnett)
Hitachi ULSI Systems Kazuyoshi Shoji*
Huawei (Jiang Xiang Zhong)
IBM (Pravin Patel)
Intel Corporation Michael Mirmak*, Arpad Muranyi*
LSI Logic (Frank Gasparik)
Mentor Graphics John Angulo*, Guy de Burgh, Ian Dodd*,
Steven McKinney*, Kim Owen*
Micron Technology Randy Wolff*, Paul Gregory*
NEC Electronics Corporation Takeshi Watanabe*, Lori Askew*,
Takuno Tsuikana*
Panasonic Atsuji Ito*
Samtec Otto Bennig*
Siemens AG (Eckhard Lenski)
Signal Integrity Software Robert Haller, Douglas Burns*, Barry Katz*,
Mike Mayer*
Sigrity Sam Chitwood*, Jing Ting, Raymond Chen*
Silicon Image (Ook Kim)
Synopsys (Warren Wong)
Teraspeed Consulting Group Bob Ross*, Scott McMorrow*,
Tom Dagostino*
Texas Instruments (Jean Claude Perrin)
Time Domain Analysis Systems Dima Smolyansky, Steve Corey*
Xilinx Ray Anderson*, Sanjay Mehta*
Zuken (Michael Schaeder)
OTHER PARTICIPANTS IN 2005:
Altera Khalid Ansari*
Bayside Design Kevin Roselle*
CelsioniX Kellee Crisafulli*
EMC Brian Arsenault*, Daniel Nilsson*,
Jason Pritchard*,
Jinhua Chen*
Enterasys Networks Fabrizio Zanella
GEIA (Chris Denham)
Green Streak Programs Lynne Green
KAW Kazuhiko Kusunoki*
Leventhal Design Roy Leventhal
Marvell Itzik Peleg*
NetLogic Eric Hsu*
North Carolina State Univ. Ambrish Varma
Silicon Bandwidth Kim Helliwell*
Sun Microsystems Gustavo Blando*
Western Digital Mohammad Ali*
In the list above, attendees at the meeting are indicated by *.
Principal members or other active members who have not attended are in
parentheses. Participants who no longer are in the organization are in
square brackets.
(New IBIS Open Forum members as of the last update to this roster include:
Agere, AMD, and Silicon Image. Welcome to the IBIS Open Forum.)
UPCOMING MEETINGS
The bridge numbers for future IBIS teleconferences are as follows:
Date Telephone Number Bridge # Passcode
February 18, 2005 1-916-356-2663 1 094-4986
March 11, 2005 DATE IBIS Summit - No bridge
March 24, 2005 JEITA-IBIS Meeting - No bridge
All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas
are typically distributed seven days before each Open Forum. Minutes
are typically distributed within seven days of the corresponding
meeting. When calling into the meeting, provide the bridge number and
passcode at the automated prompts. If asked by an operator, please
request to join the IBIS Open Forum hosted by Michael Mirmak.
For international dial-in numbers, please contact Michael Mirmak.
NOTE: "AR" = Action Required.
--------------------------------MINUTES-----------------------------------
INTRODUCTIONS AND MEETING QUORUM
The IBIS Open Forum Summit was held in Santa Clara, California at the
Westin Hotel during the DesignCon2005 Conference. Fifty-four participants
from twenty-seven organizations attended.
The notes below capture some of the content and discussions. The meeting
presentations and other documents are uploaded at:
http://www.ibis-information.org/summits/jan05/
Michael Mirmak opened the meeting. Michael thanked the IEC, Cadence, and
Cisco Systems for their sponsorship of the meeting. Michael thanked the
presenters and participants for attending.
Due to time constraints, Michael asked for introductions of the meeting
participants to be done later in the day. The group was well-attended by a
cross-section of the IBIS community, including semiconductor vendors,
service providers, EDA tool vendors, and IBIS users.
Michael asked if there were any new issues or discussion items to add to
the agenda. No issues were raised.
PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions. These
notes capture some of the content and discussion. More details are
available in the documents uploaded to the location noted above.
IBIS CHAIR'S REPORT AND ROADMAP UPDATE
Michael Mirmak, Intel Corporation
Michael Mirmak delivered an overview of the current state of the IBIS Open
Forum and its activities. Highlights included that the IBIS 4.1 parser is
near completion, ICM 1.1 is closed, membership is trending to 30 members for
2005, IBIS 3.2 reballoting for EIA approval is nearly complete, the IBIS
4.0 cookbook will be completed in Q2 2005, and IBIS has a strong web
presence. Future IBIS activities include IBIS 4.1 parser completion and
ICM 1.1 review, publishing, and EIA/ANSI balloting. Michael mentioned that
the next IBIS version (4.2) should not be revolutionary due to parser
licensing costs. He then showed the IBIS timeline through Q2 2006.
JEITA-IBIS CONTACT MEETING IN JAPAN
Atsuji Ito, Panasonic
Michael Mirmak introduced Atsuji Ito, the JEITA Chair from Panasonic who
presented information on JEITA. JEITA has developed an EDA model for
digital consumer electronics and automotive applications. Sixteen major
companies are members of JEITA. Atsuji then presented an overview of the
JEITA IBIS Event to be held in Tokyo, Japan on March 24, 2005.
IBIS QUALITY COMMITTEE REPORT
Kim Helliwell, Silicon Bandwidth, Inc.
Kim Helliwell presented an overview of the IBIS Quality Committee work.
Goals include a rating system that is easy to understand and adopt that
covers all sections of the IBIS specification and leverages prior work from
the Accuracy Committee. Kim showed defined quality levels of 0, 1, 2a, 2b,
and 3. Current status is that the checklist and kit are complete including
an example. A current task is to identify a list of additional software
checks that can be added to the Golden Parser. Kim requested the help of
people to use the checklist and provide feedback.
AN INITIAL CASE STUDY FOR BIRD95 - ENHANCING IBIS FOR
SSO POWER INTEGRITY SIMULATION
Sam Chitwood, Raymond Chen, Jiayuan Fang, Sigrity Inc.
Sam Chitwood presented a BIRD95 case study. He showed simulations using
HSPICE transistor models versus HSPICE-IBIS and Sigrity Speed2000 IBIS
simulations. He showed that pre-driver current was not represented except
with the transistor model. Crowbar current could be approximated fairly
well if all 4 V-t tables were present in the model. He said that the
objective of BIRD95 is to improve IBIS models to facilitate accurate SSO and
other power integrity simulations. BIRD95 adds current versus time tables
to the IBIS file. BIRD95 recommends three parasitic current extractions.
Sam stressed that crowbar current is load dependent, while pre-driver
current is independent of final loading conditions. He showed results of an
improved IBIS model with pre-driver current added in parallel with the
pullup/pulldown currents. A realistic power distribution model was added,
and there were differences. Then, he added a new compensation capacitor for
the power and ground parasitics to maximize SSO correlation with realistic
Power Distribution System models. Sam highlighted that algorithm research
would need to be done for simulating crowbar currents of arbitrary loads.
He said that BIRD95 showed great promise. Arpad Muranyi pointed out that
gate modulation effects from power supply droop still seem to be missing
from BIRD95 improvements.
BIRD95 AND POWER INTEGRITY VALIDATION USING HSPICE
Syed Huq, Vinu Arumugham, Dr. Zhiping Yang, Cisco Systems, Inc
Syed Huq began by presenting some history of BIRD95 development. The EDA
industry was challenged by the power distribution network panel at
DesignCon2004 to solve power integrity analysis. BIRD42.3 was leveraged for
BIRD95. Two tasks of BIRD95 are to solve the SSN simulation challenge using
IvsT tables and to connect to the core model using ICEM.
Dr. Zhiping Yang then presented technical data. He said that current IBIS
models ignore pre-drive current, do not model on-die parasitic capacitance
between power and ground, ignore crossbar current or do not model it
correctly, and either over- or under-estimate the power noise. Using an
HSTL driver model, he showed VDDQ current profiles with various loading
conditions comparing the transistor simulation to a standard IBIS model, an
IBIS model with Ivst tables added, and an IBIS model with IvsT and power to
ground impedance modeled. It was concluded that BIRD95 could be easily
implemented in EDA tools. Also, it was very important to properly model
on-die impedance between the power and ground supplies.
BIRD95 TECHNICAL DISCUSSION - ALL
Syed Huq, Vinu Arumugham, Dr. Zhiping Yang, Cisco Systems, Inc
Don Telian asked of Cisco to please look into sharing the spice files used
in their analysis. Todd Westerhoff asked if IC vendors would know how to
include and/or extract power supply parasitics. It was requested that a
detailed methodology be made available for extracting the on-die parasitics
from a black box spice model. It was discussed whether BIRD95 was trying to
solve power integrity, signal integrity, or both. The consensus is that we
are trying to solve signal integrity issues such as SSN through better
modeling of the power supplies. Syed Huq then presented the differences
between BIRD95 and BIRD95.1. Arpad Muranyi mentioned that he would like to
see C_comp added to the example circuit schematic.
IBIS POWER/GROUND MODELING OF LSI CORE LOGIC WITH HIGH
PIN COUNT PACKAGE FOR EMI AND PI
Norio Matsui, Dileep Divekar, and Neven Orhanovic,
Applied Simulation Technology
Hiroshi Wabuka, NEC
Norio Matsui presented how non-ideal current issues manifest themselves as
EMI issues in the core logic and I/O of chips as well as SSN in the I/Os.
Non-ideal power and ground structures are found at various levels of the
design from the core logic through the package to the PCB to the connectors.
Extraction of core logic models for EMI simulation can be done through
measurements or CAD models. Matsui showed examples of EMI simulation using
frequency domain models and using time domain models. He demonstrated how
non-ideal power and ground structures need ICM and IBIS 4.1. He introduced
the idea of model order reduction and the tradeoffs of model size versus
accuracy.
MODELING PRE/DE-EMPHASIS BUFFERS WITH [DRIVER SCHEDULE]
Arpad Muranyi, Intel Corporation
Arpad Muranyi began with history of the [Driver Schedule] keyword.
Pre/de-emphasis buffers started to appear around 2001. Implementation of
the pre/de-emphasis buffer model in IBIS can be done with two scheduled
buffer models for the main and boost buffers. The main buffer uses two
zero ON delay parameters to represent an equivalent of the normal, straight
through operation of the main buffer. The boost buffer uses two OFF delay
parameters with delay values equal to the width of a bit. This is
equivalent to a one bit delayed, inverted operation of the boost buffer.
Arpad talked about pros and cons of this technique including C_comp issues.
He pointed out that this technique extends the life of legacy IBIS.
MODELING COMPLEX I/OS WITH IBIS 4.1
Donald Telian, Cadence Design Systems
Donald Telian highlighted how HSPICE, AMS, and SPICE models are becoming
more prevalent, and IBIS is not always able to accurately model these
formats. Don interviewed many people who see HSPICE usage increasing.
They want to see [External Model] HSPICE hooks, but HSPICE is also not seen
as a long term solution, because it is too slow. So, there is much
opportunity for behavioral models to win back support. Behavioral models
must be fast to simulate, protect IP, be template based, work in many tools,
and have links to IC design. AMS models are unfamiliar to most, however
there are many positives. He asked if IBIS has thought about IP protection
of AMS models. He talked about how spice macromodeling is very powerful,
and IBIS now has this capability in IBIS 4.1. He recommends removing the
Berkeley SPICE barrier. It was recommended that Donald write a BIRD to
encompass this proposal.
STACKED PACKAGE MODELING WITH IBIS VERSION 4.1
Tom Dagostino and Bob Ross, Teraspeed Consulting Group
Bob Ross presented an analysis on stacked package modeling techniques. To
model a complex package, they setup models as [External Circuit]s and
extracted lossy, coupled interconnect structure linked by [External Circuit]
to SPICE and a [Circuit Call]. They found that no tools could simulate the
multi-lingual model. Alternative approaches included use of EBD modeling,
ICM, and vendor-specific models; however, these were not deemed acceptable.
PRACTICAL ISSUES IN ENABLING A CORPORATE IBIS LIBRARY
Todd Westerhoff, Cisco Systems, Inc
Todd Westerhoff began by highlighting the fact that many IBIS models have
significant quality problems. The goal of a corporate SI library is to move
SI analysis from the realm of the specialist to the engineer's desktop. He
highlighted an incoming inspection process, driving quality issues back to
device vendors, managing library data, library directory structure, and
model naming strategies. He talked about the role of scriptware in library
model management. He concluded that bringing SI to the masses will require
a centralized library strategy.
SEARCHING THE WWW FOR SPICE AND IBIS
Kellee Crisafulli, CelsioniX, Inc.
Kellee Crisafulli mentioned disadvantages to the IBIS group website
structure. He talked about successes and failures of using Google to
search for models from various vendors. He proposed a website that could be
created to specialize in searching for simulation models and displaying
model validation results. CelsionX has started working on a prototype of
this website idea and needs help in determining if this project is viable
and useful. Kellee requested that the IBIS committee donate an IBISCHK
source-code license for the project.
NEXT MEETING
The next IBIS Open Forum teleconference has been scheduled for February 18,
2005 from 8:00 AM to 10:00 AM US Pacific Time. A vote is scheduled for
BIRD96. The next IBIS Summit will be held March 11, 2005 at DATE. The
JEITA-IBIS meeting will be held March 24, 2005.
============================================================================
NOTES
IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046
michael.mirmak@intel.com
Senior Analog Engineer, Intel Corporation
FM6-45
1900 Prairie City Rd.
Folsom, CA 95630
VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475
rrwolff@micron.com
Simulation Engineer, Micron Technology, Inc.
8000 S. Federal Way
Mail Stop: 1-711
Boise, ID 83707-0006
LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363
lwang@cadence.com
Senior Member, Technical Staff, Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, CA 01824
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400
bob@teraspeed.com
Staff Scientist, Teraspeed Consulting Group
10238 SW Lancaster Road
Portland, OR 97219
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