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IBIS INTERCONNECT TASK GROUP
http://www.eda.org/ibis/interconnect_wip/    
Mailing list: ibis-interconnect@freelists.org  
Archives at http://www.freelists.org/archive/ibis-interconn/  
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Attendees from June 3 Meeting
ANSYS                                                                   Curtis Clark*
Cadence Design Systems                              Bradley Brim
Cisco                                                                      David Siadat
Intel Corp.                                                           Michael Mirmak*                       
Keysight Technologies                                   Radek Biernacki*
Mentor Graphics                                              Arpad Muranyi*
Micron Technology                                         Justin Butterfield, Randy Wolff
Signal Integrity Software                              Walter Katz*
Teraspeed Labs                                                Bob Ross*
University of Aveiro in Portugal                 Wael Dghais       

No patents were declared.
  
Michael Mirmak noted, as part of Opens, that he understood the earlier GND discussions would be 
moved to the IBIS-ATM meetings.  Radek Biernacki added that A_gnd would be part of the available 
nodes in the interconnect proposal under discussion in the Interconnect Task Group.
Bob Ross noted that the A_gnd node was not going to be recommended, but would not be 
prohibited.  Michael replied that an explicit treatment of A_gnd should be included in Draft 20.  Arpad 
suggested dealing with GND and referencing more broadly after discussions on the Interconnect 
proposal are closed.  

The team reviewed the existing Draft 19; some of the background material of the BIRD may be moved 
into the main body of the document.  Much of the team discussion will be embedded as comments in 
the next released Draft.

Radek asked whether Circuit Call is allowed to describe packages.  Arpad replied not, that only on-die 
interconnect is part of Circuit Call.  Bob added that one can theoretically zero out the package model 
and put the relevant information in the Circuit Call block.  

The team agreed that [Define Package Model] is permitted to co-exist with this proposal, but cannot 
overlap descriptions of Pins, Die Pads, or Terminals; [Pin Mapping] relationships are less clear, but 
should not overlap the same Pins, etc. either.  Arpad asked whether [External Circuit] can coexist in the 
same way.  Michael suggested this was true, so long as [Node Declarations] does not have to be 
complete.  Arpad agreed, noting that completeness only constrains [Pin Mapping].  

The team discussed whether “param” as a term was appropriate, or whether a new term should be 
adopted.   Bob stated that, if the syntax is different, the name should be different, as a preference.

The next meeting will continue in-document editing.