adding: Verilog-A element library, HSPICE test/ (stored 0%)
  adding: Verilog-A element library, HSPICE test/V_test.va (deflated 62%)
  adding: Verilog-A element library, HSPICE test/CCCSdiv.sp (deflated 68%)
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  adding: Verilog-A element library, HSPICE test/IO_test.va (deflated 69%)
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  adding: Verilog-A element library, HSPICE test/VCVSdiv_test.va (deflated 66%)
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  adding: Verilog-A element library, HSPICE test/TriSTATE_test.va (deflated 69%)
  adding: Verilog-A element library, HSPICE test/CCCSdiv_test.va (deflated 67%)
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  adding: Verilog-A element library, HSPICE test/CCCSpwl.sp (deflated 68%)
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  adding: Verilog-A element library, HSPICE test/CECVSpwl.sp (deflated 67%)
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  adding: Verilog-A element library, HSPICE test/VCVSmax_test.va (deflated 66%)
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  adding: Verilog-A element library, HSPICE test/VCVSmult.sp (deflated 68%)
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  adding: Verilog-A element library, HSPICE test/CCVSdiv.sp (deflated 68%)
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  adding: Verilog-A element library, HSPICE test/CCVSmin.sp (deflated 68%)
  adding: Verilog-A element library, HSPICE test/CCCSsum_test.va (deflated 67%)
  adding: Verilog-A element library, HSPICE test/OPENSOURCE.sp (deflated 66%)
  adding: Verilog-A element library, HSPICE test/VCCSsum_test.va (deflated 66%)
  adding: Verilog-A element library, HSPICE test/VCVSmax.sp (deflated 69%)
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  adding: Verilog-A element library, HSPICE test/CCVSmult.sp (deflated 68%)
  adding: Verilog-A element library, HSPICE test/CCCSmax.sp (deflated 68%)
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  adding: Verilog-A element library, HSPICE test/CCVSsum.sp (deflated 68%)
  adding: Verilog-A element library, HSPICE test/VCCSpwl.sp (deflated 68%)
  adding: Verilog-A element library, HSPICE test/CCVSpwl_test.va (deflated 64%)
  adding: Verilog-A element library, HSPICE test/VCVSdiv.sp (deflated 68%)
  adding: Verilog-A element library, HSPICE test/CCVSabs.sp (deflated 68%)
  adding: Verilog-A element library, HSPICE test/VECVSpwl.sp (deflated 67%)
  adding: Verilog-A element library, HSPICE test/VCCSmax_test.va (deflated 66%)
  adding: Verilog-A element library, HSPICE test/TCCSpwl_test.va (deflated 61%)
  adding: Verilog-A element library, HSPICE test/CCVSdly_test.va (deflated 63%)
  adding: Verilog-A element library, HSPICE test/CCCSmax_test.va (deflated 66%)
  adding: Verilog-A element library, HSPICE test/VCCSmax.sp (deflated 69%)
  adding: Verilog-A element library, HSPICE test/VCVSmult_test.va (deflated 66%)
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  adding: Verilog-A element library, HSPICE test/IO_OPENSOURCE.sp (deflated 66%)
  adding: Verilog-A element library, HSPICE test/C_test.va (deflated 62%)
  adding: Verilog-A element library, HSPICE test/CECCSpwl_test.va (deflated 64%)
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  adding: Verilog-A element library, HSPICE test/CCVSsum_test.va (deflated 66%)
  adding: Verilog-A element library, HSPICE test/VCVSabs_test.va (deflated 64%)
  adding: Verilog-A element library, HSPICE test/VCVSpwl.sp (deflated 68%)
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  adding: Verilog-A element library, HSPICE test/IO_OPENSINK_test.va (deflated 67%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/ (stored 0%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/disciplines.vams (deflated 79%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/ODT_to_VccGND_INPUT_data.dat (deflated 54%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/No_ODT_IO_OPENSINK_data.dat (deflated 67%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/No_ODT_OUTPUT_data.dat (deflated 74%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/ODT_to_VccGND_IO_data.dat (deflated 76%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/constants.vams (deflated 53%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/ODT_to_GND_IO_data.dat (deflated 75%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/IBIS_macro_library.va (deflated 94%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/ODT_to_GND_OUTPUT_data.dat (deflated 75%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/ODT_to_Vcc_OUTPUT_data.dat (deflated 76%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/ODT_to_GND_INPUT_data.dat (deflated 54%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/No_ODT_IO_data.dat (deflated 74%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/ODT_to_Vcc_IO_data.dat (deflated 75%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/ODT_to_Vcc_INPUT_data.dat (deflated 52%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/No_ODT_IO_OPENSOURCE_data.dat (deflated 68%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/No_ODT_INPUT_data.dat (deflated 57%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/ODT_to_VccGND_OUTPUT_data.dat (deflated 76%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/No_ODT_OPENSINK_data.dat (deflated 67%)
  adding: Verilog-A element library, HSPICE test/Macro_lib/No_ODT_OPENSOURCE_data.dat (deflated 68%)
  adding: Verilog-A element library, HSPICE test/CCVSmax_test.va (deflated 66%)
  adding: Verilog-A element library, HSPICE test/C.sp (deflated 68%)