adding: Sample Verilog-A prede-emphasis buffer data/ (stored 0%)
  adding: Sample Verilog-A prede-emphasis buffer data/VT_data_ODT_Vcc_GND.dat (deflated 73%)
  adding: Sample Verilog-A prede-emphasis buffer data/IV_data_ODT_GND.dat (deflated 68%)
  adding: Sample Verilog-A prede-emphasis buffer data/VT_data_ODT_GND.dat (deflated 69%)
  adding: Sample Verilog-A prede-emphasis buffer data/VT_data_no_ODT.dat (deflated 69%)
  adding: Sample Verilog-A prede-emphasis buffer data/IV_data_ODT_Vcc_GND.dat (deflated 70%)
  adding: Sample Verilog-A prede-emphasis buffer data/IV_data_no_ODT.dat (deflated 68%)
  adding: Sample Verilog-A prede-emphasis buffer data/IV_data_ODT_Vcc.dat (deflated 68%)
  adding: Sample Verilog-A prede-emphasis buffer data/VT_data_ODT_Vcc.dat (deflated 68%)