Upcoming IBIS Events
Scheduled IBIS Meetings

SPI 2018 - IEEE Signal and Power Integrity Workshop

 IBIS SUMMIT:      Friday, May 25, 2018 (tentative)
 LOCATION:         Le Quartz
                   Square Beethoven, 60 Rue du Ch√Ęteau, 29210
                   Brest, France
 ROOM:             Meridienne
 PURPOSE:          Solicit and Exchange IBIS Model Related Information
                   and Ideas
 CO-SPONSORS:      IBIS Open Forum
                   If your company would be interested in sponsoring 
                   this event, please contact Mike LaBonte.
 CONTACTS:         Lance Wang for IBIS summit Meeting
 AGENDA:           TBD
 SPI 2018:         Tuesday May22 - Friday May 25, 2018
 SPI2018 URL:      https://spi2018.sciencesconf.org/

Likely IBIS Meetings


 ROOM:             TBD
 LOCATION:         Santa Clara Convention Center
                   Santa Clara, CA

 SPONSORS:         TBD

 CONTACTS:         Mike LaBonte     email
                   Bob Ross         email

 EDICONUSA 2018:   October 17-19, 2018
 EDICONUSA URL:    http://www.ediconusa.org/

EPEPS 2018 - IEEE 25th Conference on Electrical Performance of Electronic Packaging and Systems

 ROOM:             TBD
 LOCATION:         San Jose Marriott
                   301 S. Market St.
                   San Jose, CA 95113, USA

 SPONSORS:         TBD

 CONTACTS:         Bob Ross         email
                   Mike LaBonte     email

 EPEPS 2018:       October 14-17, 2018
 EPEPS URL:        http://www.epeps.org/

Asian IBIS Summit (Shanghai), 2017

 IBIS SUMMIT:      Monday, November 13, 2017  8:30 - 17:00
 ROOM:             Ballroom ABC
 LOCATION:         Parkyard Hotel Shanghai
                   699 Bibo Road
                   Zhangjiang Hi-Tech Park
                   Shanghai 201203
                   P.R. China
 URL:              Parkyard Hotel Shanghai

 PRIMARY SPONSOR:  Huawei Technologies
 SPONSORS:         Cadence Design Systems
                   IO Methodology
                   Mentor, a Siemens Business
                   MostecEDA (SPISim)
                   ZTE Corporation

 ANNOUNCEMENT:     Chinese
 CONTACTS:         Lance Wang       email
                   Bob Ross         email

Asian IBIS Summit (Taipei), 2017

 IBIS SUMMIT:      Wednesday, November 15, 2017, 9:00 - 16:30
 ROOM:             Ballroom F (3rd floor)
 LOCATION:         Sherwood Hotel
                   111 Min Sheng E Road, Sec. 3
                   Taipei, Taiwan
 URL:              Sherwood Hotel

 SPONSORS:         IO Methodology
                   Peace Giant (SPISim)

 CONTACTS:         Lance Wang       email
                   Bob Ross         email

Asian IBIS Summit (Tokyo), 2017

 IBIS SUMMIT:      Friday, November 17,  2017, 12:30 - 17:00
 ROOM:             UDX4F NEXT2
 LOCATION:         Akihabara UDX Bldg.
                   4-14-1, Sotokanda, Chiyoda-Ku
                   Tokyo 101-0021, Japan.
 URL:              Akihabara UDX Building (Japanese)
                   Akihabara Crossfield Conference Center (English)

 PRIMARY SPONSORS: Japan Electronics and Information Technology Industries
                     Association (JEITA)
                   IBIS Open Forum
 SPONSORS:         TBD

 ANNOUNCEMENT:     http://www.ibis.org/summits/nov17c/announcement_japanese.pdf
 CONTACTS:         Bob Ross          email
                   Mitsuharu Umekawa email

DesignCon 2018 IBIS Summit

 IBIS SUMMIT:      Friday, February 2, 2018, 08:00 to 17:00
 LOCATION:         Santa Clara Convention Center
                   5101 Great America Parkway
                   Santa Clara, CA
 ROOM:             209

 URL:              Santa Clara Convention Center

 SPONSORS:         IBIS Open Forum
                   Cadence Design Systems
                   Keysight Technologies
                   Mentor, a Siemens Business

 CONTACTS:         Lance Wang for registration
                   Mike LaBonte for submission of presentations
 DesignCon Site: Santa Clara Convention Center, Santa Clara, CA   
 DesignCon URL: http://www.designcon.com/
                "DesignCon is the premier conference for chip, board and
                 systems design engineers in the high speed communications
                 and semiconductor communities. Through technical paper sessions,
                 tutorials, industry panels, product demos and exhibits,
                 attendees will gather the latest theories,methodologies,
                 techniques and advanced design tools related to all aspects

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