DATE: 03/15/06 SUBJECT: March 10, 2006 EIA IBIS Open Forum European Summit Minutes VOTING MEMBERS AND 2006 PARTICIPANTS Actel (Prabhu Mohan) Agere (Nirav Patel) AMD (Wasim Ullah), Tadashi Arai Ansoft Corporation Michael Brenneman Applied Simulation Technology Fred Balistreri Cadence Design Systems Lance Wang Cisco Systems Syed Huq, Mike Labonte, AbdulRahman Rafiq, Pedo Miran, Salman Jiva, Gurpreet Hundal, Todd Westerhoff Fluent (Chetan Desai) Freescale (Jon Burnett) Green Streak Programs Lynne Green Hitachi ULSI Systems Kazuyoshi Shoji* Huawei Technologies (Xiangzhong Jiang) Integrated Circuit Systems (ICS) (Dan Clementi) Intel Corporation Michael Mirmak, Arpad Muranyi*, Stephen Peters, Vishram Pandit LSI Logic (Frank Gasparik), Kim Helliwell Praveen Soora Marvell (Itzik Peleg) Mentor Graphics John Angulo, Ian Dodd, Gary Pratt, Guy de Burgh, Simon Vines* Micron Technology Randy Wolff NEC Electronics Corporation Takeshi Watanabe* Panasonic Atsuji Ito* Samtec (Corey Kimble) Siemens AG Eckhard Lenski*, Manfred Maurer*, Katja Koller*, Klaus Huebner*, Heinz-Hartmut Ibowski*, Flavio Maggioni*, Roberto Preatoni* Siemens Medical David Lieby Signal Integrity Software Barry Katz, Douglas Burns, Mike Mayer, Walter Katz Sigrity Sam Chitwood Silego (Joe Froniewski) Silicon Image (Ook Kim) STMicroelectronics (Antonio Girardi) Synopsys Andy Tai, Ted Mido Teraspeed Consulting Group Bob Ross Texas Instruments Otis Gorley, Richard Ward Xilinx (Ray Anderson) Zuken Michael Schaeder*, Ralf Bruening* OTHER PARTICIPANTS IN 2006: Agilent Sanjeev Gupta Altera Khalid Ansari Amkor Technology Nozad Karim Apple Computer Zhiping Yang Betty TV Stephanie Goedecke* Bosch Ingo Doerr*, Jurgen Hasch* EFM Ekkehard Miersch* Dell Aubrey Sparkman Force10 Networks Robert Badal GEIA (Chris Denham) Infineon Radovan Vuletic*, Minka Gospodinova* Christian Sporrer*, Amir Motamedi* KAW Kazuhiko Kusunoki* Lynguent Andrew Levy* Politecnico di Torino Igor Stievano* Rambus Nirmal Jain Samsung Heeseok Lee SimLab Heiko Grubrich* Vectronix AG Luca Giacotto* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. UPCOMING MEETINGS The bridge numbers for future IBIS teleconferences are as follows: Date Telephone Number Bridge # Passcode March 10, 2006 1-916-356-2663 3 987-3862 All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas are typically distributed seven days before each Open Forum. Minutes are typically distributed within seven days of the corresponding meeting. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international dial-in numbers, please contact Michael Mirmak. NOTE: "AR" = Action Required. --------------------------------MINUTES----------------------------------- INTRODUCTIONS AND MEETING QUORUM The European IBIS Summit Meeting was held all day at the ICM conference center in Munich, Germany. About 27 people from 16 companies and institutes attended. The notes below (thanks to Eckhard Lenski) capture some of the meeting content and discussions. The meeting presentations and other material are uploaded at: http://www.eda.org/pub/ibis/summits/mar06/ Ralf Bruening opened the meeting. EDA vendors, model users, and semiconductor groups were all well represented. Ralf thanked the co-sponsors Mentor Graphics, Siemens, and Zuken for sharing the meeting expenses. Ralf proposed changing the agenda to add an ad-hoc presentation by Kazuyoshi Kusunoki on the IBISIndicator(TM) tool. Everybody agreed. PRESENTATIONS AND DISCUSSION TOPICS The rest of the meeting consisted of presentations and discussions. These notes capture some of the content and discussions. More details are in the uploaded documents. SIEMENS IBIS GROUP UPDATE 2006 Eckhard Lenski, Siemens AG, Germany Eckhard Lenski reported that the Siemens IBIS Group (SIG) had decided to create a web page under the Siemens link: http://www.siemens.com. This page will help to describe the requirements on model quality that Siemens needs. Here the user shall also find short descriptions of common model problems and how to solve them. While set up for internal Siemens usage, this page is planned to be open to the public. JEITA EDA - WG ACTIVITY AND STUDY OF INTERCONNECT MODEL, PART-2 Takeshi Watanabe, NEC Electronics Corporation, Atsuji Ito, Panasonic, and Kazuhiko Kusunoki, KAW/Keihin Artwork, Japan (Expanded from Part-1 initially given on December 6, 2005) Kazuhiko Kunusoki provided an overview in which areas the EDA models are widely used. The two most important areas are the digital consumer electronics and automobile electronics. One objective of JEITA is to have a standardized EDA model for use in many applications. More problems are being encountered with electromagnetic interference (EMI), signal integrity (SI) and power integrity (PI) as application frequencies are increasing. Kazuhiko described nine main components for which EDA models are used/needed. Kazuhiko then gave an overview of the JEITA EDA working group. He stated that 15 companies are members. In the near future, the main focus will be on interconnect modeling, IBIS models for passive components and connectors, and on joint JEITA-IBIS meetings for interchange of experiences. The models for interconnect are very important for technologies like DDR and PCI-Express. Different test fixtures have been developed (for connectors, transmission lines, vias, and passive components), and comparisons between measurements and simulations are forthcoming and will be presented at the next meeting. Kazuhiko continued with future plans of a JEITA IBIS model portal. This portal could be compared with a fully-equipped kitchen with ingredients, machines, cookbooks, etc. The latest IBIS Cookbook will be translated into Japanese. Other potential future content include descriptions of simulation tools, a model library, and training material. Kazuhiko mentioned that an IBISIndicator(TM) tool (shown later) has been developed for IBIS model checking, correction, visualization and creation. He closed by discussing studies for interconnect modeling progress and problems with S-parameters, SPICE or RLGC matrices. In response to a question, Kazuhiko stated that the IBISIndicator(TM) is available in Japanese and English. FIRST STEPS WITH [EXTERNAL MODEL] IN IBIS Katja Koller, Siemens AG, Germany Katja Koller discussed some aspects for using HSPICE/VHDL-AMS over IBIS. More detailed process, voltage, and temperature (PVT) can be simulated. Other features such as pre-emphasis, ODT, SSN, and analog parts might be easier to model. She showed the primary use of [External Model] with HSPICE and VHDL-AMS. The parts of an external model are the model call, ports, control signals, internal parameters, and some IBIS parameters. Katja shared some experiences with a SPICE based tool that supports a shared environment with HSPICE. She liked having measurement parameters such as Vinh, Vinl, etc. from IBIS. She noted that Berkeley SPICE models were rarely available versus HSPICE models. However some HSPICE models require NDA's. She also noted some vendor-specific limitations such as having complex library management or having the temperature fixed at 25 degrees C. Similarly, she shared some experiences with VHDL-AMS. A large template collection of models and language flexibility for logic control provide positive advantages. Also, simulation is faster than with SPICE. Analog/passive components are easily modeled. However, few VHDL-AMS models are available, and all simulators seem to have undocumented bugs that cause project delays while being resolved. Temperature control is usually missing. A simple parser is not available. Katja concluded that HSPICE or VHDL-AMS models are most suitable for the critical nets, but take longer to simulate. VHDL_AMS are not readily available. Some tools have problems or unique features, and new quality checks are needed. Arpad Muranyi responded to a question about switching inside a model by stating that there are two levels. One is a top-level, like a SPICE netlist to initiate the switching in the tool. The second is an equation level where the switching equations are inside the model (and the tool algorithms are not used). The range of models supported by vendors was discussed. Users would like the IC vendors to support all formats (IBIS, SPICE, VHDL-AMS, S-parameters, etc.). However all formats would have to be checked for correctness. This is a time-consuming task. IBIS INDICATOR - A NEW IBIS VALIDATION TOOL Kazuyoshi Kusonoki, KAW, Japan Kazuyoshi Kunusoki introduced the validation tool, IBISIndicator(TM), by stating that IBIS text files are sometimes very large. Editing and fixing defective files becomes difficult. Since IBIS is well-established, a validation tool should be useful for industrial IBIS users including IBIS beginners. Some features were discussed and demonstrated. IBISIndicator displays IBIS information such as table current strength, voltage supplies, and rise and fall times. The interface looks like a cockpit with gauges. The tool checks and displays for non-monotonic errors for each table. Summed table checks such as for combining [Pullup] and the clamp tables is scheduled for the next release. Currently 20 checks at three different levels exist, and some errors can be automatically fixed. Kazuyoshi showed both the unfixed and fixed displays for non-monotonic data. Both the rising and falling waveforms can be displayed together. Several other features exit. An overview of parameters such as V_fixture, R_fixture, etc. is available. Pin mapping associations for different supply voltages can be shown and should be useful for FPGA pinouts. Data sheet information can be entered. Furthermore, the IBIS models can be simulated with the given test structures. INTRODUCTION TO THE IBIS MACRO MODEL LIBRARY Arpad Muranyi, Intel Corporation (Initially given on February 9, 2006) Arpad Muranyi noted that the macro model library effort started about one year ago. He showed four levels of library hierarchy. The first level is the IBIS pointer to the rest of the model (like a wrapper). The second level contain the templates, which can be described as a netlist for the parts/macros available in the model. The third level is a list of the parts used from the library. The fourth level contains the blocks in terms of the analog portions of *AMS or in native SPICE elements. The library itself contains 36 elements, including resistors, capacitances, inductors, voltage and current sources, a T-line and eight IBIS buffers. This complete library is available on the IBIS website. Also, a test suite for different tools is available. One test suite is for Verilog-A using HSPICE with the Verilog-A feature. Another suite is for VHDL-AMS using the SMASH simulator. Also Arpad mentioned that a Perl script is a available for conversion of I-V and V-T tables into the correct Vxx-AMS format. Arpad discussed the test suite architecture. It consists of three parts. First is the top level SPICE files, including the simulation control statements. Next are the macro model templates in Vxx-AMS to instantiate the building blocks from the library. The library is the third part of the test suite. Arpad showed the downloaded file suite available from the website. He showed the similarities and differences between the Verilog-A(MS) and the VHDL-A(MS) file systems. He also showed some examples for a resistor, a capacitor, and an IBIS I/O buffer. The 5 V swing in the example was for demonstration purposes only. Some questions followed. Arpad explained that these models could be delivered to the customer using the hierarchical IBIS model where the top (or [External Model]) would be IBIS, and the bottom would be the Vxx-AMS section. Arpad responded to a question about modeling series elements in [External Model] with two possibilities. One is to use [External Model] connected like IBIS. The other is to use [External Circuit] connected using arbitrary nodes. So series elements can be readily handled. Arpad concluded that in the future the committee wants feedback and wants to determine if some elements are missing. There will probably be more work for models in the frequency domain. SSO SIMULATION WITH IBIS Manfred Maurer, Siemens AG, Germany (Initially given on February 9, 2006) Manfred Maurer noted that IBIS currently does not have the information to accurately simulate Simultaneous Switching Outputs (SSO). However, only a few new parameters are needed for accurate SSO simulation. Two effects exist for SSO. One is for 'm' outputs to switch while one quiet line is checked. The other is to investigate the dynamic switching outputs for changing timing behavior. This is due to internal Vcc and GND shifts caused by the switching. In 2000, Dr. Bernhard Unger showed that additional multipliers for the [Pullup] and [Pulldown] tables could be used to analyze SSO. With the additional multiplier, Kssn, modeling factors related to the voltage drop changes between Vcc and GND, the SSO results are very accurate. Manfred explained that the transistors had been working in the saturation region. In more recent IC devices, Manfred showed that there are big mismatches in SSO with the year 2000 approaches. The transistors are operating in the linear region. Additional parameters are needed beyond the static Kssn factors. He introduced a dynamic td_RC parameter and showed better correlation with the transistor model simulations. However, some mismatch remains. Manfred investigated using independent parameters for the [Pullup] and [Pulldown] tables. Further improvement is needed, possibly available through the BIRD95 and BIRD97 approaches. Manfred responded to a question that changing the C values (an added Cpre prestage capacitance in the 2000 model) did not produce better results. Manfred noted that he also got different results from the two parts he used in the tests. LUNCH/DISCUSSION (30 Minutes) The group recessed for a brief working lunch. ICEM (IC EMISSION MODELING) CURRENT STATUS & RESULTS FROM VARIOUS R+D PROJECTS Ralf Bruening, Zuken, Germany (Uploaded, but not presented because of agenda adjustments and time limitations) INFLUENCE OF STIMULI ON THE RISING FALLING WAVEFORM TIMING Eckhard Lenski, Siemens AG, Germany Eckhard Lenski noted that when he worked with an SSTL-25 buffer, it checked out without any problems and looked reasonable. However, when the buffers were configured in differential mode, the waveform crossing values were very unsymmetrical and not in the mid-range voltage. He investigated the reason for this by working with both the IBIS buffer and SPICE model. He noted that the core section and output section of the SPICE model had different supply voltages. He had observed that his results were sensitive to the input stimuli speed. So he created some test cases and performed a set of tests described below to understand how rise-time and voltage swing affected the differential symmetry. The specific test cases were for 1.8 V and 2.5 V stimuli (designated as 1p8v, 2p5v) and rise times of 1 ps and 1 ns (designated as 1ps, 1ns). The first results showed that for the models created with the 1 ps rise time, the results were independent of the voltage swing. The rise and fall starting points were the same. However, with 1 ns rise times, both the starting points were delayed and were also sensitive to whether the input swing was 2.5 V or 1.8 V. Furthermore, there was also a difference between the results for a 1p8v swing and a 2p5v swing. The rising edges for 2p5v swing did start before the rising edges for the 1p8v swing. The opposite occurs for the falling edges where the 2p5v stimuli swing starts after the 1p8v swing. Closer investigation gave the result that this difference is coming from the different time points when the stimuli is crossing the internal 0p9v threshold. So the time between the different starting points for rising (and falling) edges is about the same time that the stimuli for a different swing crosses the internal threshold. Eckhard continued by investigating the influence on the operating frequency of the IBIS models with different stimuli under typ, min, and max conditions. For a given frequency, half the period time is needed for the rising and falling edges. He observed that a model created with 1 ps stimuli had no problem operating at 333 MHz under typ conditions. A 1 ns stimuli cannot be used for this frequency. Similar problems occur for min and max models. Eckhard concluded with several suggestions. As a rule of thumb, the stimuli rise and fall time should be about 100 times faster than the rise time and fall time of the output buffer. Also, the IBIS Cookbook needs to suggest more clearly the stimuli needed for waveform extraction. IC MACROMODELS FROM ON-THE-FLY TRANSIENT RESPONSES Flavio Canavero, Ivan Maio, and Igor Stievano, Politecnico di Torino, Italy Igor Stievano noted that while traditional IBIS models are sufficient for many applications, advanced models to deal with increasingly complex interactions are needed. These interactions can be described by equations for non-linear parametric models and linked into tools using IBIS 4.1. He gave a short overview from his earlier presentations about how M(Pi)log models are created from suitable voltage stimuli and the measured voltage and current responses. For example, I-V data static current is extracted from several voltage sweeps over the range of interest. This produces the first guess. Then weighting signals (or parameters) are computed from applying a lumped load to the switched output. Igor noted that different sources and load conditions are necessary. The measurements for M(Pi)log models can be done on-the-fly from parts with a circuit. The IC will be stimulated by a random pattern, the output buffer currents and voltages are measured. This process does work only over a limited range, not the whole range. A perturbing element such as a long stub allows exploration over a wider region of solution space. The process takes into account the logic state and time dependencies to again produce a good set of weighting signals. Igor showed good experimental correlation. The three steps are summarized. First the device is stimulated and the reactions are measured. Second, the port responses are fed into the algorithm for computing the model signals. Finally, the resulting model equations are implemented in SPICE or VHDL-AMS. Igor showed the process with the SN74ALVCH16973 by modeling it both without and with a noisy environment. Both environments produced similar results. Igor concluded with a list of advantages. The device can be measured in normal operating conditions. Test fixtures are not needed. Static characteristics can be extracted from transient measurements on-the-fly. During a discussion Igor pointed out that package effects are also captured in the model behavior. He is looking for a solution for taking out the package effects. HDL AND IBIS 4.1 MODELS IN A FUNCTIONAL DDR MEMORY INTERFACE ANALYSIS Simon Vines, Mentor Graphics, United Kingdom (Note, this presentation is expanded from the one given on February 9, 2006 by Randy Wolff, Micron Technology, USA) Simon Vines described the project to do a complete simulation of a DDR memory interface. The simulation should consider overshoot/undershoot violations, setup and hold timing violations, pattern dependent crosstalk, and slew dependent timing calculations. The project was approached by combining HDL functional models with IBIS I/O models from Micron Technology, such that HDL checks take care of timing, and IBIS models handle basic electrical checks. This is done using IBIS 4.1. Simon showed an overview of the PCB layout. Its topology uses an FPGA for a chipset/controller. The layout database contains PCB traces, vias, passive components and connectors. The layout terminates at the memory. The chipset uses digital code to generate the stimuli pattern for the write cycle. Then the memory works in the corresponding read cycle. Simon showed analog results for data, clock and address signals and digital results for the address and clock signals. He also showed a zoomed combined view. The model was implemented using the [Circuit Call] keyword to call the model of the whole memory part. This is not officially allowed by IBIS. Simon noted that a paper is available on this topic. VHDL-AMS allows new features to be easily modeled that are difficult or impossible to model with IBIS. He mentioned that ODT could be modeled in four lines of code. He also showed some of the VHDL-AMS code. The circuit must describe all 80 pins of the memory device. The instantiation of models all worked. The simulation took five to ten minutes. Five man-weeks were needed for modeling, setup, etc., but this would be reduced to one week for the next layout. In response to a question about vendor changes in parts, Simon noted that the IBIS model must be changed, but the same HDL model could still be used. Simon responded to a question on DIMM module crosstalk analysis that the module looked like a normal board and was handled using multiboard analysis techniques. ACCURACY OF IBIS MODELS WITH REACTIVE LOADS Arpad Muranyi, Intel Corporation (Initially given on February 9, 2006) Arpad provided an overview of the basic V-I and V-t table structure of the IBIS model. He explained, how the V-t tables are used to generate partially ON V-I tables in a manner that converted to K-t table scaling coefficients. The calculators are done by Kirchoff's law for currents at one node in terms of two equations and two unknowns. This is valid only for static conditions. In newer technologies like PCI-Express, there is a series capacitor for AC coupling. The equations do not account for this. Similarly, inductance is omitted. Both parts have time dependent differential terms that need to be added to the equation. The capacitance term is I = C*dV/dt, and the inductance term is V = L*dI/dt. When the time constant of C_series and R_fixture is large, the two equations can be considered as static. Arpad noted that more investigation is needed. However, missing time dependent terms might provide a reason for differences between SPICE and IBIS simulations. OPEN/DISCUSSIONS Future package model formats were discussed since simple lumped RLC models are no longer appropriate. Arpad Muranyi stated that the ICM specification has become an official GEIA standard and could be the solution. Presently no connection between IBIS and ICM exist. Vendors must provide the connection. One vendor supports ICM, but its approach is constrained to assuming an ideal ground. Some companies which produce field solver tools are working on this problem. CLOSING TOPICS Ralf Bruening thanked the participants for attending and the presenters for providing a fine set of presentations. Ralf also thanked the sponsors for keeping the European IBIS Summit Meeting active. Ralf mentioned that there was much interaction during the breaks and that this was one of the most successful meetings, and even better than last year. NEXT MEETING The next IBIS Open Forum teleconference will be held March 10, 2006 from 8:00 AM to 10:00 AM US Pacific Time. ============================================================================ NOTES IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-3788 michael.mirmak@intel.com Server Platform Technical Marketing Engineer, Intel Corporation FM5-79 1900 Prairie City Rd. Folsom, CA 95630 VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475 rrwolff@micron.com Simulation Engineer, Micron Technology, Inc. 8000 S. Federal Way Mail Stop: 01-711 Boise, ID 83707-0006 LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363 lwang@cadence.com Senior Member, Technical Staff, Cadence Design Systems, Inc. 270 Billerica Road Chelmsford, MA 01824 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400 bob@teraspeed.com Staff Scientist, Teraspeed Consulting Group 10238 SW Lancaster Road Portland, OR 97219 This meeting was conducted in accordance with the GEIA Legal Guides and GEIA Manual of Organization and Procedure. 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