EGG #2 -- controlled rise-time devices

Hello Fellow IBISIANS --

     In this egg I am proposing a method that allows IBIS to handle
controlled rise-time devices by describing the output waveform with a
a 'percent voltage' vs 'percent time' curve. First, some background:

     The past month or so I have been trying to model a set of buffers
that have edge rate control via phased turn on of multiple output
transistors. As shown in FIG 1, a set of transistors are ganged together
and turned on at slightly different times, thus shaping the output
waveform as shown in FIG 2.

                  
                  _
                   |
        ___________|___________O pin
        | | |
       _| _| _|
  g1 -| g2 -| g3 -|
      |_ |_ |_
        | | |
       _|_______|_______|__
              gnd

        FIG 1. -- example pulldown stage with phased turn on.

        | ***************
        | * *
        | * *
        | ** *
 volts | * *
        | * *
        | * *
        | ** *
        | * *
        | * *
        | * *
        |_______________________________________________________

                               time

         FIG 2. -- example shaped output waveform

     As shown in FIG 2, the output waveform is not a smooth curve.
Using the standard Dv/Dt and IV curve methodology an IBIS model was
not able to successfully predict either the time it takes to reach
logic thresholds or the maximum Dv/Dt of the waveform (critical for
determining the maximum allowable stub length in a layout topology.)
The only way I have found to build an accurate model of the buffer
is to scale the I-V curve of the buffer with a second curve that
describes the 'percent output voltage' (%V) vs. the "percent rise
time (%T).

Theory:
     The problem is that the standard I-V curve, taken under what are
effectively DC conditions, do not describe the I-V characteristics
of the device while the output is in transition. As transistors
are turning on or off, the I-V characteristics change. The idea behind
the %V - %T methodology is that, while the output transistors are turning
on (i.e. the output is in transition), the I/V characteristics of the
output can be described as a *scaled* version of the final DC I-V
characteristics. For example, suppose the output took 3ns to reach its
final DC I-V value, each transistor was identical (1/3 the total drive
strength) and each transistor turned on 1ns apart. After 1ns the output
has obtained 33% of its final DC strength, after 2ns it has obtained 66% of its
final DC strength and after 3ns it is at 100% of its final DC strength.
The output I/V characteristics have been effectively scaled by a specific
percentage, based on the 100% rise time of the output waveform. A
(really) simplified behavioral model of this type looks like the following:

                                                _
            --|----------------------------|---|_| output pin
              | ____________ ___ _|_
              |__| V-I curve |---| M | | |
                 | generator | | U |---| | |
              ___| | | L | | V | (current source)
              | |___________| |_T_| |___|
              | ___________ | |
   time ramp-----| %V - %T |______| |
   generator | | curve | |
              | |__________| |
              | |
            __|____________________________|____

     The I-V curves are obtained as always, the %V - %T curve is obtained
by picking points off a graph (or table) of the output waveform. Both
the I-V and %V - %T data is used to determine the final output current.

                
Results:
     I've modeled a real live example of a buffer of this type using
Quad Design's version of the %V - %T methodology. With the Quad software
I am able to match the output waveform almost exactly -- for a given
resistive load (i.e. get a %V - %T curve from a transistor level
simulation, enter the data into the Quad model, then do a Quad simulation
into the same load and compare results). As one changes the load the
waveforms (Quad vs. transistor level) began to diverge, but in any case
it is still far more accurate that the standard IBIS model. I also have
preliminary results using an HSPICE model provided by Arpad Muranyi here
at Intel. They look good but more testing is needed.

Issues:
     This methodology has worked for a specific set of load topologies
under a rather narrow range of Zo. I have not had a chance to try
capacitive loads, nor try extreme ranges of Zo. My guess is that
this method also works for edge rate control devices where the gate
waveform is shaped, but I don't have a design to try it out on.
I also don't have any data on how this method works if the transistors
are not scaled linearly (HINT HINT -- anybody got any of these designs and
would be willing to share simulation results with the group?)
What I am looking for is feedback that addresses the usability, accuracy
and robustness of this methodology. With your feedback I'd like to get an
official bird together and posted in the next week or so, with an eye
towards getting this into rev 2.0.

                Best Regards,
                Stephen Peters
                Intel Corp.
Received on Thu Apr 7 17:39:31 1994